IPR-PCI/MT32 Altera, IPR-PCI/MT32 Datasheet - Page 277

• Manufacturer Part Number: IPR-PCI/MT32
• Description: IP CORE Renewal Of IP-PCI/MT32
• Manufacturer: Altera
• Type: MegaCorer

Specifications of IPR-PCI/MT32

• Software Application: IP CORE, Interface And Protocols, PCI
• Supported Families: Arria GX, Arria II GX, Cyclone, Stratix
• Core Architecture: FPGA
• Core Sub-architecture: Arria, Cyclone, Stratix
• Rohs Compliant: NA
• Function: PCI Compiler, Master/Target, 32 bit
• License: Renewal License
• Lead Free Status / RoHS Status: na
• Lead Free Status / RoHS Status: na

Figure 7–4. PCI-Avalon Bridge Block Diagram Managing the PCI Master/Target Peripheral Mode
Altera Corporation
January 2011
Processor
Master/
Arbiter
Device
Target
PCI
Bus
Host
PCI
Bus
PCI
MegaCore
Function
PCI
You can customize the Master/Target mode by specifying one of the
performance profiles. Refer to
Control Register Access Avalon Slave
The PCI-Avalon bridge provides a rich set of user-accessible
control/status registers. Implementing the registers is optional except
when using the:
■
■
The Avalon Configuration tab of the PCI Compiler wizard allows you to
enable the control/status registers and specify access to them via the
interconnect. Refer to
The control/status registers can be accessed from any Avalon-MM
master device including PCI-Avalon bridge master ports. If you want to
access the control/status registers from a PCI bus master device, you
must use the SOPC Builder GUI to connect the Avalon-MM ports to the
Control Register Access Avalon Slave port. Refer to
PCI Host-Bridge Device mode
Dynamic Avalon-to-PCI address translation option
Controller
Controller
Master/Target Peripheral Mode
Master
Target
PCI
PCI
PCI-Avalon Bridge
PCI Compiler Version 10.1
Prefetchable
Prefetchable
Bridge Logic
Master
Bridge
Bridge
Logic
Logic
Non-
PCI
PCI
“Avalon Configuration” on page
“Performance Profiles” on page
Prefetchable
Prefetchable
Avalon Slave
PCI Bus
Avalon
Access
Avalon
Master
Master
Non-
Interconnect
System
Fabric
Functional Description
6–16.
Figure
7–11.
Peripheral
Peripheral
Peripheral
Peripheral
Master
Slave
Master
Slave
7–5.
7–9