IPR-PCI/MT32 Altera, IPR-PCI/MT32 Datasheet - Page 89

• Manufacturer Part Number: IPR-PCI/MT32
• Description: IP CORE Renewal Of IP-PCI/MT32
• Manufacturer: Altera
• Type: MegaCorer

Specifications of IPR-PCI/MT32

• Software Application: IP CORE, Interface And Protocols, PCI
• Supported Families: Arria GX, Arria II GX, Cyclone, Stratix
• Core Architecture: FPGA
• Core Sub-architecture: Arria, Cyclone, Stratix
• Rohs Compliant: NA
• Function: PCI Compiler, Master/Target, 32 bit
• License: Renewal License
• Lead Free Status / RoHS Status: na
• Lead Free Status / RoHS Status: na

Altera Corporation
January 2011
Note to
(1)
cache[7..0]
cmd_reg[6..0]
stat_reg[6..0]
Table 3–3. Parameterized Configuration Register Signals
Table 3–4. PCI Command Register Output Bus (cmd_reg[6..0]) Bit Definition
Bit Number
This signal is added for compliance with the PCI Local Bus Specification, Revision 3.0.
Name
0
1
2
3
4
5
6
Table
3–4:
Output
Output
Output
int_dis
mstr_ena
perr_ena
serr_ena
mem_ema
mwi_ena
Bit Name
io_ena
Type
Parameterized Configuration Register Signals
Table 3–3
parameterized configuration register signals.
Table 3–4
(1)
–
–
–
Polarity
summarizes the PCI local interface signals for the
shows definitions for the command register output bus bits.
PCI Compiler Version 10.1
I/O accesses enable. Bit 0 of the command register.
Memory access enable. Bit 1 of the command register.
Master enable. Bit 2 of the command register. This signal is
reserved for
Memory write and invalidate enable. Bit 4 of the command register.
Parity error response enable. Command register bit 6.
System error response enable. Command register bit 8.
Interrupt disable. Command register bit 10.
Cache line-size register output. The
the same as the configuration space cache line-size register.
The local-side logic uses this signal to provide support for
cache commands.
Command register output. The
the important signals of the configuration space command
register to the local side. Refer to
Status register output. The
the important signals of the configuration space status
register to the local side. Refer to
pci_t64
and
Description
pci_t32
Description
stat_reg[6..0]
cmd_reg[6..0]
.
Table
Table
cache[7..0]
Functional Description
3–4.
3–5.
bus drives
bus drives
bus is
3–15