IPR-PCI/MT32 Altera, IPR-PCI/MT32 Datasheet - Page 141

• Manufacturer Part Number: IPR-PCI/MT32
• Description: IP CORE Renewal Of IP-PCI/MT32
• Manufacturer: Altera
• Type: MegaCorer

Specifications of IPR-PCI/MT32

• Software Application: IP CORE, Interface And Protocols, PCI
• Supported Families: Arria GX, Arria II GX, Cyclone, Stratix
• Core Architecture: FPGA
• Core Sub-architecture: Arria, Cyclone, Stratix
• Rohs Compliant: NA
• Function: PCI Compiler, Master/Target, 32 bit
• License: Renewal License
• Lead Free Status / RoHS Status: na
• Lead Free Status / RoHS Status: na

Altera Corporation
January 2011
Burst Memory Write Target Transactions
The sequence of events in a burst write transaction is the same as for a
single-cycle memory write target transaction. However, in a burst write
transaction, more data is transferred and both the local-side device and
the PCI master can insert wait states.
Figure 3–16
transaction with five data phases. The 64-bit extension signals are not
applicable to the pci_mt32 and pci_t32 functions. The PCI master
writes five QWORDs to the PCI MegaCore function during clock cycles 6
through 10. The PCI MegaCore function transfers the same data to the
local side during clock cycles 7 through 11. Additionally,
shows the lt_tsr[9] signal asserted in clock cycle 4 because the master
device has the framen and irdyn signals asserted, thus indicating a
burst transaction.
A burst transaction is indicated by the PCI MegaCore function if it detects
both irdyn and framen are asserted on the PCI side after the address
phase. The PCI MegaCore function asserts lt_tsr[9] to indicate a burst
transaction. If lt_tsr[9] is not asserted during a transaction, it
indicates that irdyn and framen have not been detected or asserted
during the transaction. Typically this event indicates that the current
transaction is single-cycle. However, this situation is not guaranteed
because it is possible for the master to delay the assertion of irdyn in the
first data phase by up to 8 clock cycles. In other words, if lt_tsr[9] is
asserted during a valid target transaction, it indicates that the impending
transaction is a burst, but if lt_tsr[9] is not asserted it may or may not
indicate that the transaction is single-cycle.
PCI Compiler Version 10.1
shows a 64-bit zero-wait state burst memory write target
Functional Description
Figure 3–16
3–67