IPR-PCI/MT32 Altera, IPR-PCI/MT32 Datasheet - Page 324

• Manufacturer Part Number: IPR-PCI/MT32
• Description: IP CORE Renewal Of IP-PCI/MT32
• Manufacturer: Altera
• Type: MegaCorer

Specifications of IPR-PCI/MT32

• Software Application: IP CORE, Interface And Protocols, PCI
• Supported Families: Arria GX, Arria II GX, Cyclone, Stratix
• Core Architecture: FPGA
• Core Sub-architecture: Arria, Cyclone, Stratix
• Rohs Compliant: NA
• Function: PCI Compiler, Master/Target, 32 bit
• License: Renewal License
• Lead Free Status / RoHS Status: na
• Lead Free Status / RoHS Status: na

Control & Status Registers
7–56
PCI Compiler User Guide
15:0
31:16 Reserved
0
1
7:2
13:8
15:14 Reserved
31:16
Table 7–24. Performance Parameters – Address 0x2C04
Table 7–25. Avalon-to-PCI Address Translation Parameters – Address 0x2C08
Bit
Bit
A2P_WRITE_CD_DEPTH
A2P_ADDR_MAP_IS_FIXED
A2P_ADDR_MAP_IS_READABLE
Reserved
A2P_ADDR_MAP_PASS_THRU_BIT
S
A2P_ADDR_MAP_NUM_ENTRIES
Name
Name
Table 7–24
Table 7–25
translation table.
Avalon-MM Interrupt Status Register
The Avalon-MM interrupt status register contains the status of various
signals in the PCI-Avalon bridge logic, and it allows Avalon-MM
interrupts to be signaled when enabled via the Avalon-MM interrupt
enable register. These registers are not intended to be accessed by the
PCI-Avalon bridge master ports. However, there is nothing in the
hardware that prevents this.
RO
RO
Access
Mode
PCI Compiler Version 10.1
lists some key performance sizing information of the core.
lists the configuration of the Avalon-to-PCI address
RO
RO
RO
RO
RO
RO
Access
Mode
Reflects the depth of the Avalon-to-PCI command and data
buffer. The software may not want to issue burst writes (via
Avalon DMA or similar) to the bridge that exceed half this
value in length. While larger bursts are supported, if the PCI
bus is slow or very busy, larger bursts may take a very long
time to complete on Avalon, preventing smaller requests
from other Avalon-MM masters from being recognized.
Backing up those other requests could slow overall
performance.
Reserved
Indicates that the Fixed Translation Table (refer to
“Avalon Configuration” on page
Indicates if the Avalon-to-PCI translation table is
readable. This bit is always set to 1.
Reserved
Indicates the number of pass-through bits (binary
encoded).
Reserved
Indicates the number of pages in the Address
Translation Table Size field.
Description
Description
6–16) is selected.
Altera Corporation
January 2011