IPR-PCI/MT32 Altera, IPR-PCI/MT32 Datasheet - Page 108

• Manufacturer Part Number: IPR-PCI/MT32
• Description: IP CORE Renewal Of IP-PCI/MT32
• Manufacturer: Altera
• Type: MegaCorer

Specifications of IPR-PCI/MT32

• Software Application: IP CORE, Interface And Protocols, PCI
• Supported Families: Arria GX, Arria II GX, Cyclone, Stratix
• Core Architecture: FPGA
• Core Sub-architecture: Arria, Cyclone, Stratix
• Rohs Compliant: NA
• Function: PCI Compiler, Master/Target, 32 bit
• License: Renewal License
• Lead Free Status / RoHS Status: na
• Lead Free Status / RoHS Status: na

Configuration Registers
3–34
PCI Compiler User Guide
11
12
13
14
15
Table 3–17. Status Register Format (Part 2 of 2)
Data
Bit
tabort_sig
tar_abrt_rec
mstr_abrt
serr_set
det_par_err
Mnemonic
Revision ID Register
Revision ID is an 8-bit read-only register that identifies the revision
number of the device. The value of this register is assigned by the
manufacturer (e.g., Altera for the PCI MegaCore functions.) For the
Altera PCI MegaCore functions, the default value of the revision ID
register is the revision number of the function. Refer to
can change the value of the revision ID register through the wizard.
Table 3–18. Revision ID Register Format
Data Bit
7..0
Read/Write
Read/write
Read/write
Read/write
Read/write
Read/write
PCI Compiler Version 10.1
Signaled target abort. This bit is set when a local peripheral
device terminates a transaction. The function automatically
sets this bit if it issued a target abort after the local side
asserted
the
Target abort. When high,
function in master mode has detected a target abort from the
current target device. This bit is driven to the local side on the
stat_reg[2]
Master abort. When high,
function in master mode has terminated the current
transaction with a master abort. This bit is driven to the local
side on the
Signaled system error. When high,
that the function drove the
address phase parity error has occurred. The function
signals a system error only if an address phase parity error
was detected and
to the local side on the
Detected parity error. When high,
that the function detected either an address or data parity
error. Even if parity error reporting is disabled (via
perr_ena
signal is driven to the local side on the
output.
Mnemonic
rev_id
stat_reg
lt_abortn
), the function sets the
stat_reg[3]
[1] output.
output.
serr_ena
Read/Write
. This bit is driven to the local side on
Read
stat_reg[4]
Definition
tar_abrt_rec
mstr_abrt
serrn
output.
was set. This signal is driven
det_par_err
det_par_err
output active, i.e., an
serr_set
stat_reg[5]
PCI revision ID
indicates that the
output.
Altera Corporation
Table
Definition
indicates that the
January 2011
indicates
3–18. You
indicates
bit. This