IPR-PCI/MT32 Altera, IPR-PCI/MT32 Datasheet - Page 6

• Manufacturer Part Number: IPR-PCI/MT32
• Description: IP CORE Renewal Of IP-PCI/MT32
• Manufacturer: Altera
• Type: MegaCorer

Specifications of IPR-PCI/MT32

• Software Application: IP CORE, Interface And Protocols, PCI
• Supported Families: Arria GX, Arria II GX, Cyclone, Stratix
• Core Architecture: FPGA
• Core Sub-architecture: Arria, Cyclone, Stratix
• Rohs Compliant: NA
• Function: PCI Compiler, Master/Target, 32 bit
• License: Renewal License
• Lead Free Status / RoHS Status: na
• Lead Free Status / RoHS Status: na

Contents
Chapter 2. Parameter Settings
Chapter 3. Functional Description
vi
PCI Compiler User Guide
Compile the Design ............................................................................................................................. 1–16
Program a Device ................................................................................................................................ 1–18
PCI Timing Support ............................................................................................................................ 1–18
Using the Reference Designs .............................................................................................................. 1–19
Parameterize PCI Compiler ................................................................................................................. 2–1
PCI MegaCore Function Settings ........................................................................................................ 2–1
Read-Only PCI Configuration Registers ............................................................................................ 2–2
PCI Base Address Registers (BARs) .................................................................................................... 2–2
Advanced PCI MegaCore Function Features .................................................................................... 2–3
Variation File Parameters ..................................................................................................................... 2–7
Functional Overview ............................................................................................................................. 3–1
PCI Bus Signals .................................................................................................................................... 3–11
PCI Bus Commands ............................................................................................................................ 3–27
Configuration Registers ...................................................................................................................... 3–28
pci_mt32 MegaCore Function Reference Design ....................................................................... 1–19
pci_mt64 MegaCore Function Reference Design ....................................................................... 1–21
Target Device Signals & Signal Assertion .................................................................................... 3–6
Master Device Signals & Signal Assertion .................................................................................... 3–9
Parameterized Configuration Register Signals .......................................................................... 3–15
Local Address, Data, Command, & Byte Enable Signals ......................................................... 3–16
Target Local-Side Signals .............................................................................................................. 3–20
Master Local-Side Signals ............................................................................................................. 3–24
Vendor ID Register ......................................................................................................................... 3–31
Device ID Register .......................................................................................................................... 3–31
Command Register ........................................................................................................................ 3–32
Status Register ................................................................................................................................ 3–33
Revision ID Register ...................................................................................................................... 3–34
Class Code Register ........................................................................................................................ 3–35
Cache Line Size Register ............................................................................................................... 3–35
Latency Timer Register .................................................................................................................. 3–36
Header Type Register .................................................................................................................... 3–36
Base Address Registers .................................................................................................................. 3–37
CardBus CIS Pointer Register ....................................................................................................... 3–40
Subsystem Vendor ID Register .................................................................................................... 3–40
Subsystem ID Register ................................................................................................................... 3–41
Expansion ROM Base Address Register ..................................................................................... 3–41
Capabilities Pointer ........................................................................................................................ 3–42
Interrupt Line Register .................................................................................................................. 3–43
Synthesis & Compilation Instructions ................................................................................... 1–20
synthesis & Compilation Instructions .................................................................................... 1–22
Optional Registers ....................................................................................................................... 2–3
Optional Interrupt Capabilities ................................................................................................. 2–4
Master Features ........................................................................................................................... 2–4
PCI Compiler Version 10.1
Altera Corporation