IPR-PCI/MT32 Altera, IPR-PCI/MT32 Datasheet - Page 110

• Manufacturer Part Number: IPR-PCI/MT32
• Description: IP CORE Renewal Of IP-PCI/MT32
• Manufacturer: Altera
• Type: MegaCorer

Specifications of IPR-PCI/MT32

• Software Application: IP CORE, Interface And Protocols, PCI
• Supported Families: Arria GX, Arria II GX, Cyclone, Stratix
• Core Architecture: FPGA
• Core Sub-architecture: Arria, Cyclone, Stratix
• Rohs Compliant: NA
• Function: PCI Compiler, Master/Target, 32 bit
• License: Renewal License
• Lead Free Status / RoHS Status: na
• Lead Free Status / RoHS Status: na

Configuration Registers
3–36
PCI Compiler User Guide
Latency Timer Register
The latency timer register is an 8-bit register with bits 2, 1, and 0 tied to
ground. The register defines the maximum amount of time, in PCI bus
clock cycles, that the PCI function can retain ownership of the PCI bus.
After initiating a transaction, the function decrements its latency timer by
one on the rising edge of each clock cycle. The default value of the latency
timer register is 0x00. Refer to
1
Header Type Register
Header type is an 8-bit read-only register that identifies the PCI function
as a single-function device. The default value of the header type register
is 0x00. Refer to
Table 3–21. Latency Timer Register Format
Table 3–22. Header Type Register Format
Data Bit
Data Bit
2..0
7..3
7..0
This register is implemented in the pci_mt64 and pci_mt32
functions only.
PCI Compiler Version 10.1
Table
Mnemonic
lat_tmr
lat_tmr
Mnemonic
header
3–22.
Table
Read/Write
Read/write
3–21.
Read/Write
Read
Read
Latency timer register
Latency timer register
Altera Corporation
PCI header type
Definition
Definition
January 2011