IPR-PCI/MT32 Altera, IPR-PCI/MT32 Datasheet - Page 181

• Manufacturer Part Number: IPR-PCI/MT32
• Description: IP CORE Renewal Of IP-PCI/MT32
• Manufacturer: Altera
• Type: MegaCorer

Specifications of IPR-PCI/MT32

• Software Application: IP CORE, Interface And Protocols, PCI
• Supported Families: Arria GX, Arria II GX, Cyclone, Stratix
• Core Architecture: FPGA
• Core Sub-architecture: Arria, Cyclone, Stratix
• Rohs Compliant: NA
• Function: PCI Compiler, Master/Target, 32 bit
• License: Renewal License
• Lead Free Status / RoHS Status: na
• Lead Free Status / RoHS Status: na

Figure 3–37. 32-Bit PCI & 64-Bit Local Side Burst Memory Read Master Transaction
Altera Corporation
January 2011
l_dato[63..32]
lm_adr_ackn
l_dato[31..0]
l_cbeni[3..0]
l_cbeni[7..4]
l_hdat_ackn
l_ldat_ackn
l_adi[31..0]
lm_tsr[9..0]
lm_req64n
cben[3..0]
ad[31..0]
lm_dxfrn
lm_lastn
lm_ackn
lm_rdyn
devseln
ack64n
framen
req64n
stopn
irdyn
trdyn
reqn
gntn
par
clk
1
000
2
3
I/O & Configuration Read Transactions
I/O and configuration read transactions by definition are 32 bits wide.
The sequence of events is the same as in a 32-bit single-cycle memory read
master transaction, as shown in
the pci_mt64 and pci_mt32 MegaCore functions, excluding the 64-bit
extension signals as noted for pci_mt32.
001
4
PCI Compiler Version 10.1
5
002
0
0
Adr
6
6
004
Adr
BE_H
BE_L
6
7
Adr-PAR
Z
008
8
Figure
D0_L
Z
9
D0-L-PAR
3–36. This figure applies to both
D1_L
D0_L
BE_L
10
D1-L-PAR
D2_L
D1_L
108
11
Functional Description
D2-L-PAR
D3_L
D2_L
12
D3-L-PAR
D3_L
Z
Z
13
000
3–107