IPR-PCI/MT32 Altera, IPR-PCI/MT32 Datasheet - Page 138

• Manufacturer Part Number: IPR-PCI/MT32
• Description: IP CORE Renewal Of IP-PCI/MT32
• Manufacturer: Altera
• Type: MegaCorer

Specifications of IPR-PCI/MT32

• Software Application: IP CORE, Interface And Protocols, PCI
• Supported Families: Arria GX, Arria II GX, Cyclone, Stratix
• Core Architecture: FPGA
• Core Sub-architecture: Arria, Cyclone, Stratix
• Rohs Compliant: NA
• Function: PCI Compiler, Master/Target, 32 bit
• License: Renewal License
• Lead Free Status / RoHS Status: na
• Lead Free Status / RoHS Status: na

Target Mode Operation
Figure 3–15. Single-Cycle Memory Write Target Transaction
Note to
(1)
3–64
PCI Compiler User Guide
This signal is not applicable to the pci_mt32 or pci_t32 MegaCore functions.
Figure
(1) l_dato[63..32]
(1) l_hdat_ackn
(1) l_beno[7..4]
(1) l_ldat_ackn
(1) ad[63..32]
(1) cben[7..4]
l_adro[31..0]
l_dato[31..0]
l_cmdo[3..0]
l_beno[3..0]
lt_tsr[11..0]
(1) ack64n
(1) req64n
cben[3..0]
3–15:
lt_framen
(1) par64
ad[31..0]
devseln
lt_dxfrn
lt_ackn
framen
lt_rdyn
stopn
irdyn
trdyn
par
clk
1
Single-cycle Memory Write Target Transactions
Figure 3–15
target transaction. The 64-bit extension signals are not applicable to the
pci_mt32 and pci_t32 MegaCore functions.
2
000
Adr
7
3
Adr-PAR
PCI Compiler Version 10.1
shows the waveform for a 64-bit single-cycle memory write
4
BE0_H
BE0_L
D0_L
D0_H
5
Adr
7
181
D0-L-PAR
D0-H-PAR
6
BE0_L
BE0_H
7
D0_H
D0_L
581
8
9
000
10
Altera Corporation
January 2011
11