IPR-PCI/MT32 Altera, IPR-PCI/MT32 Datasheet - Page 165

• Manufacturer Part Number: IPR-PCI/MT32
• Description: IP CORE Renewal Of IP-PCI/MT32
• Manufacturer: Altera
• Type: MegaCorer

Specifications of IPR-PCI/MT32

• Software Application: IP CORE, Interface And Protocols, PCI
• Supported Families: Arria GX, Arria II GX, Cyclone, Stratix
• Core Architecture: FPGA
• Core Sub-architecture: Arria, Cyclone, Stratix
• Rohs Compliant: NA
• Function: PCI Compiler, Master/Target, 32 bit
• License: Renewal License
• Lead Free Status / RoHS Status: na
• Lead Free Status / RoHS Status: na

Altera Corporation
January 2011
The pci_mt64 and pci_mt32 functions support the following 32-bit
PCI transactions:
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A master operation begins when the local-side master interface asserts
the lm_req64n signal to request a 64-bit transaction or the lm_req32n
signal to request a 32-bit transaction. The PCI function asserts the reqn
signal to the PCI bus arbiter to request bus ownership. When the PCI bus
arbiter grants the PCI function bus ownership by asserting the gntn
signal, the local side is alerted and must provide the address and
command.
Once the PCI MegaCore function has acquired mastership of the PCI bus,
the function asserts framen to indicate the beginning of a bus
transaction, which is referred to as the address phase. During the address
phase, the function drives the address and command signals on the
ad[31..0] and cben[3..0] buses. If the local side requests a 64-bit
transaction when using the pci_mt64 function, the function asserts the
req64n and framen signals at the same time. After the PCI MegaCore
function master device has completed the address phase, the master
waits for the target devices on the bus to decode the address and claim the
transaction by asserting devseln. With a 64-bit transaction, the target
device asserts ack64n and devseln at the same time if it can accept the
64-bit transaction. If the target device does not assert ack64n, the master
device completes a 32-bit transaction.
Both the pci_mt64 and pci_mt32 functions support single-cycle and
memory burst transactions. In a read transaction, data is transferred from
the PCI target device to the local-side device. In a write transaction, data
is transferred from the local side to the PCI target device. A memory
transaction can be terminated by the local side or by the PCI target device.
When the PCI target terminates the transaction, the local side is informed
of the conditions of the termination by specific bits in the lm_tsr[9..0]
bus. The function treats memory write and invalidate, memory read
multiple, and memory read line commands in a similar manner to the
corresponding memory write/read commands. Therefore, the local side
must implement any special handling required by these commands. The
function outputs the cache line size register value to the local side for this
purpose.
32-bit burst memory read/write
32-bit single-cycle memory read/write
Configuration read/write
I/O read/write
PCI Compiler Version 10.1
Functional Description
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