IPR-PCI/MT32 Altera, IPR-PCI/MT32 Datasheet - Page 312

• Manufacturer Part Number: IPR-PCI/MT32
• Description: IP CORE Renewal Of IP-PCI/MT32
• Manufacturer: Altera
• Type: MegaCorer

Specifications of IPR-PCI/MT32

• Software Application: IP CORE, Interface And Protocols, PCI
• Supported Families: Arria GX, Arria II GX, Cyclone, Stratix
• Core Architecture: FPGA
• Core Sub-architecture: Arria, Cyclone, Stratix
• Rohs Compliant: NA
• Function: PCI Compiler, Master/Target, 32 bit
• License: Renewal License
• Lead Free Status / RoHS Status: na
• Lead Free Status / RoHS Status: na

PCI Master Operation
7–44
PCI Compiler User Guide
Notes to
(1)
(2)
(3)
(4)
(5)
(6)
(7)
PMW
DRR
DWR
DRC
DWC
Table 7–15. Summary of Ordering in the PCI-to-Avalon Direction
Spec refers to the PCI Local Bus Specification, Revision 3.0, published by PCI-SIG.
Impl refers to the implementation of this passing rule in the PCI-Avalon bridge.
PMWs and DRRs cannot pass other PMWs in the PCI-to-Avalon Command/Write Data buffer. Ordering logic will
prevent PMWs that hit prefetchable BARs and PMWs that hit non-prefetchable BARs from passing each other.
The ordering logic prevents DRCs from passing PMWs
Avalon-MM does not provide any mechanism to stop accepting reads separately from writes, so there is no way
to make PMWs, DRCs (or other DRRs) pass DRRs. However, since Avalon-MM provides completely separate
paths for master and slave transactions, the PCI requirements for this passing do not apply.
PMWs and DRRs in the PCI-to-Avalon Buffers are allowed to pass DRCs in the Read Response buffers.
Avalon-MM requires the DRCs (Read Responses) be returned in the order the requests were made. Note, however,
that DRCs may actually be returned in a different order than they completed on the PCI bus.
Table
No
No
No
No
Yes/ No
Spec(1) Impl(2)
7–15:
PMW
No(3)
No(3)
No(3)
No(4)
No(4)
Table 7–15
PCI-to-Avalon direction. The entries in this table describe whether a type
in a row may pass a type in a column. The table uses the following
terminology: "No" means a type may not pass another type, "Yes/No"
means a type may pass the other type, but does not have to, and "Yes"
means that a type must pass another type to avoid deadlocks.
Yes
Yes/ No
Yes/ No
Yes
Yes
Spec
DRR
PCI Compiler Version 10.1
specifies the ordering rules and behavior for the
No(5)
No(5)
No(5)
No(5)
No(5)
Impl
Yes
Yes/ No N/A
Yes/ No
Yes
Yes
Spec
DWR
N/A
No(5)
N/A
No
Impl
Yes
Yes/ No
Yes/ No
Yes/ No
Yes/ No No
Spec
DRC
Yes(6)
Yes(6)
Yes(6)
No(7)
Impl
Altera Corporation
Yes
Yes/ No Yes
Yes/ No No
Yes/ No No
Yes/ No No
Spec
January 2011
DWC
Yes
Impl