IPR-PCI/MT32 Altera, IPR-PCI/MT32 Datasheet - Page 172

• Manufacturer Part Number: IPR-PCI/MT32
• Description: IP CORE Renewal Of IP-PCI/MT32
• Manufacturer: Altera
• Type: MegaCorer

Specifications of IPR-PCI/MT32

• Software Application: IP CORE, Interface And Protocols, PCI
• Supported Families: Arria GX, Arria II GX, Cyclone, Stratix
• Core Architecture: FPGA
• Core Sub-architecture: Arria, Cyclone, Stratix
• Rohs Compliant: NA
• Function: PCI Compiler, Master/Target, 32 bit
• License: Renewal License
• Lead Free Status / RoHS Status: na
• Lead Free Status / RoHS Status: na

Master Mode Operation
3–98
PCI Compiler User Guide
10
11
12
Table 3–38. Zero-Wait State Burst Memory Read Master Transaction (Part 3 of 3)
Clock
Cycle
Because
and
last data phase is completed on the PCI side on the rising edge of clock cycle 11.
On the local side, the function continues to assert
has registered data from the PCI side on the previous cycle and is ready to send the data to the local
side master interface. Because
asserted in the current cycle, the function asserts
l_ldat_ackn
available on the
The function continues to assert
has occurred on the PCI bus during the previous clock cycle.
On the PCI side,
transaction on the PCI side is completed. There will be no more PCI data phases.
On the local side, the function continues to assert
has registered data from the PCI side on the previous cycle and is ready to send the data to the local-
side master interface. Because
asserted in the current cycle, the function asserts
l_ldat_ackn
is valid. The local side has now received three 64-bit words of data.
Because the local side has received all the data that was registered from the PCI side, the local side
can now deassert
the PCI side to the local side,
The function continues to assert
has occurred on the PCI bus during the previous clock cycle.
The function deasserts
completed. Therefore,
req64n
lm_lastn
are deasserted, while
, and
, and
l_dato
irdyn
lm_rdyn
l_hdat_ackn
was asserted and a data phase was completed in the previous cycle,
l_hdat_ackn
lm_ackn
lm_tsr
,
devseln
bus. The local side has now received two valid 64-bit data.
. Otherwise, if there is still some data that has not been transferred from
PCI Compiler Version 10.1
lm_rdyn
lm_rdyn
lm_rdyn
lm_tsr[8]
lm_tsr[8]
[3], informing the local side that the data transfer mode is
and
,
irdyn
ack64n
signals indicate to the local side that data on the
lm_dxfrn
signals indicate to the local side that another valid data is
must continue to be asserted.
was asserted in the previous cycle and
was asserted in the previous cycle and
and
, and
informing the local side that a successful data transfer
informing the local side that a successful data transfer
Event
trdyn
lm_ackn
lm_ackn
lm_dxfrn
trdyn
lm_dxfrn
are also deasserted.
are asserted. This action indicates that the
are deasserted, indicating that the current
, informing the local side that the function
, informing the local side that the function
. The assertion of the
. The assertion of the
Altera Corporation
lm_ackn
lm_ackn
lm_dxfrn
lm_dxfrn
January 2011
l_dato
framen
is
is
,
,
bus