IPR-PCI/MT32 Altera, IPR-PCI/MT32 Datasheet - Page 122

• Manufacturer Part Number: IPR-PCI/MT32
• Description: IP CORE Renewal Of IP-PCI/MT32
• Manufacturer: Altera
• Type: MegaCorer

Specifications of IPR-PCI/MT32

• Software Application: IP CORE, Interface And Protocols, PCI
• Supported Families: Arria GX, Arria II GX, Cyclone, Stratix
• Core Architecture: FPGA
• Core Sub-architecture: Arria, Cyclone, Stratix
• Rohs Compliant: NA
• Function: PCI Compiler, Master/Target, 32 bit
• License: Renewal License
• Lead Free Status / RoHS Status: na
• Lead Free Status / RoHS Status: na

Target Mode Operation
3–48
PCI Compiler User Guide
Target Read Transactions
This section describes the behavior of the PCI MegaCore functions in the
following types of target read transactions:
■
■
■
Memory Read Transactions
The PCI MegaCore functions support the following types of matched bus
width and mismatched bus width memory read transactions in target
mode:
■
■
■
1
For all memory read transactions, the following sequence of events is the
same:
1.
2.
3.
Memory read
I/O read
Configuration read
Single-cycle memory read
Burst memory read
Mismatched bus width memory read
The address phase occurs when the PCI master asserts framen (and
req64n in the case of a 64-bit transaction) and drives the address on
ad[31..0] and the command on cben[3..0]. Asserting req64n
indicates to the target device that the master device is requesting a
64-bit data transaction.
Turn-around cycles on the ad bus occur during the clock cycle
immediately following the address phase. During turn-around
cycles the PCI side drives correct byte enables on the cben bus for
the first data phase but tri-states the ad bus. This process is
necessary because the PCI agent driving the ad bus changes during
read cycles.
If the address of the transaction matches the memory range
specified in a base address register, the PCI MegaCore function
turns on the drivers for the ad bus, devseln, trdyn, stopn, and
par (as well as par64 and ack64n for 64-bit transactions) in the
following clock cycle.
Mismatched bus-width transactions are 32-bit PCI transactions
performed by the pci_mt64 and pci_t64 MegaCore
functions.
PCI Compiler Version 10.1
Altera Corporation
January 2011