IPR-PCI/MT32 Altera, IPR-PCI/MT32 Datasheet - Page 231

• Manufacturer Part Number: IPR-PCI/MT32
• Description: IP CORE Renewal Of IP-PCI/MT32
• Manufacturer: Altera
• Type: MegaCorer

Specifications of IPR-PCI/MT32

• Software Application: IP CORE, Interface And Protocols, PCI
• Supported Families: Arria GX, Arria II GX, Cyclone, Stratix
• Core Architecture: FPGA
• Core Sub-architecture: Arria, Cyclone, Stratix
• Rohs Compliant: NA
• Function: PCI Compiler, Master/Target, 32 bit
• License: Renewal License
• Lead Free Status / RoHS Status: na
• Lead Free Status / RoHS Status: na

Altera Corporation
January 2011
4.
5.
Modify the target transactor model memory range. The target
transactor reserves a 1-KByte memory array by default. On reset,
this memory array is initialized by the trgt_tranx_mem_init.dat file.
Refer to
this file.
You can modify the memory instantiated by the target transactor
model by changing the address_lines value and the mem_hit_range
value to correspond to the value specified by address_lines. For
example, if address_lines is 1024, the target transactor instantiates a
1-KByte memory array that corresponds to a memory hit range of
000-3FF Hex. Refer to
for more information.
Simulate the testbench for the desired time period.
PCI Compiler Version 10.1
“FILE IO section” on page 4–13
“Target Transactor (trgt_tranx)” on page 4–12
for more information about
PCI Compiler User Guide
Testbench
4–21