IPR-PCI/MT32 Altera, IPR-PCI/MT32 Datasheet - Page 316

• Manufacturer Part Number: IPR-PCI/MT32
• Description: IP CORE Renewal Of IP-PCI/MT32
• Manufacturer: Altera
• Type: MegaCorer

Specifications of IPR-PCI/MT32

• Software Application: IP CORE, Interface And Protocols, PCI
• Supported Families: Arria GX, Arria II GX, Cyclone, Stratix
• Core Architecture: FPGA
• Core Sub-architecture: Arria, Cyclone, Stratix
• Rohs Compliant: NA
• Function: PCI Compiler, Master/Target, 32 bit
• License: Renewal License
• Lead Free Status / RoHS Status: na
• Lead Free Status / RoHS Status: na

Control & Status Registers
7–48
PCI Compiler User Guide
0x0000-0x0FFF
0x1000-0x1FFF
0x2000-0x2FFF
0x3000-0x3FFF
Table 7–16. Control and Status Register Address Spaces
Address Range
Registers typically intended for access by PCI processors only. This includes PCI interrupt
enable controls, write access to the PCI-to-Avalon mailbox registers, and read access to
Avalon-to-PCI mailbox registers.
Avalon-to-PCI address translation tables. Depending on the system design, these may be
accessed by PCI processors, Avalon processors, or both.
Read only registers that reflect various configuration parameters of the implementation.
Depending on the system design these may be accessed by PCI processors, Avalon
processors, or both.
Registers typically intended for access by Avalon processors only. This includes Avalon-MM
interrupt enable controls, I/O and configuration request control registers, write access to the
Avalon-to-PCI mailbox registers, and read access to PCI-to-Avalon mailbox registers.
Because all accesses come from Avalon-MM (requests from the PCI bus
are routed through Avalon-MM), there is no hardware controlling which
processors access which regions. However, enforcement via processor
software is designed to be straightforward.
sub-regions.
The data returned to a read issued to any undefined address in this range
is unpredictable.
PCI Compiler Version 10.1
Address Space Usage
Table 7–16
describes the four
Altera Corporation
January 2011