IPR-PCI/MT32 Altera, IPR-PCI/MT32 Datasheet - Page 111

• Manufacturer Part Number: IPR-PCI/MT32
• Description: IP CORE Renewal Of IP-PCI/MT32
• Manufacturer: Altera
• Type: MegaCorer

Specifications of IPR-PCI/MT32

• Software Application: IP CORE, Interface And Protocols, PCI
• Supported Families: Arria GX, Arria II GX, Cyclone, Stratix
• Core Architecture: FPGA
• Core Sub-architecture: Arria, Cyclone, Stratix
• Rohs Compliant: NA
• Function: PCI Compiler, Master/Target, 32 bit
• License: Renewal License
• Lead Free Status / RoHS Status: na
• Lead Free Status / RoHS Status: na

Altera Corporation
January 2011
Base Address Registers
The PCI function supports up to six BARs. Each BAR (BARn) has identical
attributes. Use the Parameterize - PCI Compiler wizard to instantiate
BARs in the function on an individual basis. BARs must be used in
sequence, starting with BAR0; one or more of the BARs in the function
must be instantiated. The logic for the unused BARs is automatically
reduced by the Quartus II software when the PCI function is compiled.
Each BAR has its own parameter BARn (where n is the BAR number). The
value for this parameter is a 32-bit hexadecimal number that can be
updated through the wizard to select a combination of the following BAR
options:
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■
■
■
1
The BAR is formatted per the PCI Local Bus Specification, Revision 3.0. Bit 0
of each BAR is read only, and is used to indicate whether the reserved
address space is memory or I/O. BARs that map to memory space must
hardwire bit 0 to 0, and BARs that map to I/O space must hardwire bit
0 to 1. Depending on the value of bit 0, the format of the BAR changes.
You can set the type of BAR through the wizard.
In a memory BAR, bits 1 and 2 indicate the location of the address space
in the memory map. You can control the location of specific BAR
addresses (i.e., whether they are mapped in 32- or 64-bit address space)
through options in the wizard. The pci_mt64 and pci_t64 functions
allow you to implement a 64-bit BAR using BAR1 and BAR0, or by using
BAR2 and BAR1. The BARn parameters will be updated accordingly.
Bit 3 of a memory BAR controls whether the BAR is prefetchable. If you
choose the prefetchable memory option for an individual BAR in the
wizard, bit 3 of the corresponding BARn parameter will be updated.
Type of address space reserved by the BAR
Location of the reserved memory
Marks the reserved memory as prefetchable or non-prefetchable
Size of memory or I/O address space reserved for the BAR
When compiling the PCI function, the Quartus II software
generates informational messages informing you of the number
and options of the BARs you have specified.
PCI Compiler Version 10.1
Functional Description
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