IPR-PCI/MT32 Altera, IPR-PCI/MT32 Datasheet - Page 319

• Manufacturer Part Number: IPR-PCI/MT32
• Description: IP CORE Renewal Of IP-PCI/MT32
• Manufacturer: Altera
• Type: MegaCorer

Specifications of IPR-PCI/MT32

• Software Application: IP CORE, Interface And Protocols, PCI
• Supported Families: Arria GX, Arria II GX, Cyclone, Stratix
• Core Architecture: FPGA
• Core Sub-architecture: Arria, Cyclone, Stratix
• Rohs Compliant: NA
• Function: PCI Compiler, Master/Target, 32 bit
• License: Renewal License
• Lead Free Status / RoHS Status: na
• Lead Free Status / RoHS Status: na

Altera Corporation
January 2011
10
11
12
13
15:14 Reserved
16
17
18
19
20
21
22
23
31:24 Reserved
Table 7–18. PCI Interrupt Status Register – Address: 0x0040 (Part 2 of 2)
Bit
PCI_TABORT_RCVD
PCI_MABORT_RCVD
PCI_SERR_SIG
PCI_PERR_DET
A2P_MAILBOX_INT0
A2P_MAILBOX_INT1
A2P_MAILBOX_INT2
A2P_MAILBOX_INT3
A2P_MAILBOX_INT4
A2P_MAILBOX_INT5
A2P_MAILBOX_INT6
A2P_MAILBOX_INT7
Name
PCI Interrupt Enable Register
By setting the corresponding bits in the PCI interrupt enable register, a
PCI interrupt can be signaled for any of the conditions registered in the
PCI interrupt status register
register has one-to-one mapping to the PCI interrupt status register.
PCI Compiler Version 10.1
RO
RO
RO
RO
N/A
RW1C
RW1C
RW1C
RW1C
RW1C
RW1C
RW1C
RW1C
N/A
Access
Mode
Reflects the current value of PCI status register bit 12,
target abort received. This bit can only be cleared
through a direct access to the PCI configuration status
register.
Reflects the current value of PCI configuration status
register bit 13, master abort received. This bit can only
be cleared through a direct access to the PCI
configuration status register.
Reflects the current value of PCI configuration status
register bit 14, system error signaled. This bit can only
be cleared through a direct access to the PCI
configuration status register.
Reflects the current value of PCI configuration status
register bit 15,
Set to 1 when the
Set to 1 when the
Set to 1 when the
Set to 1 when the
Set to 1 when the
Set to 1 when the
Set to 1 when the
Set to 1 when the
(Table
7–19). The PCI interrupt enable
PERR
A2P_MAILBOX0
A2P_MAILBOX1
A2P_MAILBOX2
A2P_MAILBOX3
A2P_MAILBOX4
A2P_MAILBOX5
A2P_MAILBOX6
A2P_MAILBOX7
Description
detected.
Functional Description
is written to.
is written to.
is written to.
is written to.
is written to.
is written to.
is written to.
is written to.
7–51