IPR-PCI/MT32 Altera, IPR-PCI/MT32 Datasheet - Page 109

• Manufacturer Part Number: IPR-PCI/MT32
• Description: IP CORE Renewal Of IP-PCI/MT32
• Manufacturer: Altera
• Type: MegaCorer

Specifications of IPR-PCI/MT32

• Software Application: IP CORE, Interface And Protocols, PCI
• Supported Families: Arria GX, Arria II GX, Cyclone, Stratix
• Core Architecture: FPGA
• Core Sub-architecture: Arria, Cyclone, Stratix
• Rohs Compliant: NA
• Function: PCI Compiler, Master/Target, 32 bit
• License: Renewal License
• Lead Free Status / RoHS Status: na
• Lead Free Status / RoHS Status: na

Altera Corporation
January 2011
Class Code Register
Class code is a 24-bit read-only register divided into three sub-registers:
base class, sub-class, and programming interface. Refer to the PCI Local
Bus Specification, Revision 3.0 for detailed bit information. The default
value of the class code register is 0xFF0000. You can change the value of
the class_code register using the Parameterize - PCI Compiler wizard.
Refer to
Cache Line Size Register
The cache line size register specifies the system cache line size in DWORDs.
This read/write register is written by system software at power-up. The
value in this register is driven to the local side on the cache[7..0] bus.
The local side must use this value when using the memory read line,
memory read multiple, and memory write and invalidate commands in
master mode. Refer to
1
Table 3–19. Class Code Register Format
Table 3–20. Cache Line Size Register Format
Data Bit
Data Bit
23..0
7..0
Table
This register is implemented in the pci_mt64 and pci_mt32
functions only.
PCI Compiler Version 10.1
3–19.
class_code
Mnemonic
Mnemonic
cache
Table
3–20.
Read/Write
Read/Write
Read/write
Read
Functional Description
Cache line size
Class code
Definition
Definition
3–35