IPR-PCI/MT32 Altera, IPR-PCI/MT32 Datasheet - Page 188

• Manufacturer Part Number: IPR-PCI/MT32
• Description: IP CORE Renewal Of IP-PCI/MT32
• Manufacturer: Altera
• Type: MegaCorer

Specifications of IPR-PCI/MT32

• Software Application: IP CORE, Interface And Protocols, PCI
• Supported Families: Arria GX, Arria II GX, Cyclone, Stratix
• Core Architecture: FPGA
• Core Sub-architecture: Arria, Cyclone, Stratix
• Rohs Compliant: NA
• Function: PCI Compiler, Master/Target, 32 bit
• License: Renewal License
• Lead Free Status / RoHS Status: na
• Lead Free Status / RoHS Status: na

Master Mode Operation
Figure 3–39. 32-Bit PCI & 32-Bit Local-Side Burst Memory Write Master Transaction
Note to
(1)
3–114
PCI Compiler User Guide
This signal is not applicable to the
Figure
(1) l_adi[63..32]
(1) l_cbeni[7..4]
(1) l_hdat_ackn
(1) l_ldat_ackn
lm_adr_ackn
l_cbeni[3..0]
lm_tsr[9..0]
l_adi[31..0]
lm_req32n
(1) ack64n
(1) req64n
cben[3..0]
ad[31..0]
lm_dxfrn
lm_lastn
lm_ackn
lm_rdyn
devseln
3–39:
framen
stopn
irdyn
trdyn
reqn
gntn
par
clk
1
000
2
Figure 3–39
side master interface requests a 32-bit transaction by asserting
lm_req32n. This figure applies to both pci_mt64 and pci_mt32,
excluding the 64-bit extension signals as noted for pci_mt32. The
pci_mt64 function does not assert req64n on the PCI side. Therefore,
the upper address ad[63..32] and the upper command/byte enables
cben[7..4] are invalid.
3
pci_mt32
001
PCI Compiler Version 10.1
4
shows the same transaction as in
MegaCore function.
5
Adr
002
0
0
7
6
D0_L
BE_L
Adr
004
7
7
Adr-PAR
D0_L
D1_L
008
8
D0-L-PAR
D1_L
BE_L
D2_L
9
Figure
D1-L-PAR
108
D2_L
10
3–42, but the local
D2-L-PAR
Altera Corporation
Z
Z
11
000
January 2011