IPR-PCI/MT32 Altera, IPR-PCI/MT32 Datasheet - Page 113

• Manufacturer Part Number: IPR-PCI/MT32
• Description: IP CORE Renewal Of IP-PCI/MT32
• Manufacturer: Altera
• Type: MegaCorer

Specifications of IPR-PCI/MT32

• Software Application: IP CORE, Interface And Protocols, PCI
• Supported Families: Arria GX, Arria II GX, Cyclone, Stratix
• Core Architecture: FPGA
• Core Sub-architecture: Arria, Cyclone, Stratix
• Rohs Compliant: NA
• Function: PCI Compiler, Master/Target, 32 bit
• License: Renewal License
• Lead Free Status / RoHS Status: na
• Lead Free Status / RoHS Status: na

Altera Corporation
January 2011
0
1
31..2
Table 3–24. I/O Base Address Register Format
Data
Bit
io_ind
Reserved
bar
Mnemonic
Read
–
Read/write
Read/Write
For example, if a 64-bit BAR on BARs 1 and 0 is implemented and the
designer indicates 8 as the maximum number of address bits to decode
on the upper BAR, the upper 24 bits [31..8] of BAR1 will be read-only
bits tied to ground. The eight least significant bits [7..0] of BAR1 are
read/write registers, and— along with bits [31..4] of BAR0—they
indicate the size of the memory. When a 64-bit memory BAR is
implemented, the remaining BARs can still be used for 32-bit memory or
I/O base address registers in conjunction with a 64-bit BAR setting. If
BARs 2 and 1 are used to implement a 64-bit BAR, BAR0 must be used as
a 32-bit memory or I/O base address register.
1
Like a memory BAR, an I/O BAR can be instantiated on any of the six
BARs available for the PCI function. The wizard offers the option to
implement a 32-bit BAR as memory or I/O and sets the bits [1..0] of
the corresponding BARn parameter accordingly. The PCI Local Bus
Specification, Revision 3.0 prevents any single I/O BAR from reserving
more than 256 bytes of I/O space. Refer to
In some applications, one or more BARs must be hardwired. The PCI
MegaCore functions allow you to set default base addresses that can be
used to claim transactions without requiring the configuration of the
corresponding BARs. The wizard allows you to implement this feature on
an individual BARn basis and sets the corresponding parameters
accordingly. When using the hardwire BAR feature, the corresponding
BARn attributes must indicate the appropriate BAR settings, such as size
and type of address space.
1
I/O indicator. The
address space. This bit must be set to 1 in the BARn parameter.
–
Base address registers.
Reserved memory space can be calculated by the following
formula: 2
and 8 = user assigned read/write register.
When implementing a hardwire BAR, the corresponding BARs
become read-only. A configuration write to the hardwired BAR
will proceed normally. However, a configuration read of
hardwired BARs will return the value set in the hardwire BARn
parameter.
PCI Compiler Version 10.1
(40 – 8)
io_ind
= 4 GBytes, where 40 = actual available registers
bit indicates that the register maps into I/O
Definition
Table
3–24.
Functional Description
3–39