IPR-PCI/MT32 Altera, IPR-PCI/MT32 Datasheet - Page 345

• Manufacturer Part Number: IPR-PCI/MT32
• Description: IP CORE Renewal Of IP-PCI/MT32
• Manufacturer: Altera
• Type: MegaCorer

Specifications of IPR-PCI/MT32

• Software Application: IP CORE, Interface And Protocols, PCI
• Supported Families: Arria GX, Arria II GX, Cyclone, Stratix
• Core Architecture: FPGA
• Core Sub-architecture: Arria, Cyclone, Stratix
• Rohs Compliant: NA
• Function: PCI Compiler, Master/Target, 32 bit
• License: Renewal License
• Lead Free Status / RoHS Status: na
• Lead Free Status / RoHS Status: na

Simulation Flow
Altera Corporation
January 2011
This section describes the simulation flow using Altera PCI testbench.
Figure 8–3
using the PCI testbench.
Figure 8–3. Typical Verification Environment Using the PCI Testbench
The simulation flow using Altera PCI testbench comprises the following
steps.
1.
1
2.
Use SOPC Builder to create your system.
f
SOPC Builder creates the pci_sim directory in your project directory
and copies all the PCI testbench files from
<path>/pci_compiler/testbench/sopc/<language>/<core> into
<project directory>/pci_sim.
Set the initialization parameters, which are defined in the master
transactor model source code. These parameters control the address
space reserved by the target transactor model and other PCI agents
on the PCI bus.
The testbench files must be edited to add the PCI transactions
that will be performed on the system. If you regenerate your
system, SOPC Builder will not overwrite the testbench files in
the pci_sim directory. If you want the default testbench files,
first delete the pci_sim directory and then regenerate your
system.
PCI Compiler Version 10.1
shows the block diagram of a typical verification environment
Testbench
For more information on creating your system using SOPC
Builder, refer to
PCI
PCI Bus
Chapter 5, Getting
Altera Device
Using SOPC Builder
System Generated
Altera PCI Testbench
PCI Compiler User Guide
Started.
Testbench
8–15