IPR-PCI/MT32 Altera, IPR-PCI/MT32 Datasheet - Page 145

• Manufacturer Part Number: IPR-PCI/MT32
• Description: IP CORE Renewal Of IP-PCI/MT32
• Manufacturer: Altera
• Type: MegaCorer

Specifications of IPR-PCI/MT32

• Software Application: IP CORE, Interface And Protocols, PCI
• Supported Families: Arria GX, Arria II GX, Cyclone, Stratix
• Core Architecture: FPGA
• Core Sub-architecture: Arria, Cyclone, Stratix
• Rohs Compliant: NA
• Function: PCI Compiler, Master/Target, 32 bit
• License: Renewal License
• Lead Free Status / RoHS Status: na
• Lead Free Status / RoHS Status: na

Altera Corporation
January 2011
Mismatched Bus-Width Memory Write Target Transactions
The following description applies only to the pci_mt64 and pci_t64
functions handling mismatched bus width memory write target
transactions.
When using the pci_mt64 or pci_t64 MegaCore functions to accept
32-bit memory write transactions, the local side data bus width is 64 bits
while the PCI data bus width is 32 bits. The pci_mt64 and pci_t64
functions transfer 32-bit data from the PCI side and drive that data to the
l_dato[31..0] bus. The pci_mt64 and pci_t64 functions decode
whether the low or high DWORD is addressed by the master device, based
on the starting address of the transaction. If the address of the transaction
is a QWORD boundary (ad[2..0] == B"000"), the first DWORD
transferred is considered the low DWORD and pci_mt64 or pci_t64
asserts l_ldat_ackn accordingly; if the address of the transaction is not
at a QWORD boundary (ad[2..0] == B"100"), the first DWORD
transferred is considered to be the high DWORD and the pci_mt64 or
pci_t64 function asserts l_hdat_ackn accordingly.
Figure 3–19
write transaction applying to the pci_mt64 and pci_t64 functions.
Refer to
write transaction using the pci_mt32 or pci_t32 function. The
sequence of events in
except for the following:
■
■
■
During the address phase (clock cycle 3) the master does not assert
req64n because the transaction is 32 bits
The MegaCore function does not assert ack64n when it asserts
devseln
The local side is informed that the pending transaction is 32 bits
because lt_tsr[7] is not asserted while lt_framen is asserted in
clock cycle 4
Figure 3–15
PCI Compiler Version 10.1
shows a 32-bit single-cycle mismatched bus width memory
for a description of a 32-bit single cycle memory
Figure 3–19
is exactly the same as in
Functional Description
Figure
3–15,
3–71