IPR-PCI/MT32 Altera, IPR-PCI/MT32 Datasheet - Page 87

• Manufacturer Part Number: IPR-PCI/MT32
• Description: IP CORE Renewal Of IP-PCI/MT32
• Manufacturer: Altera
• Type: MegaCorer

Specifications of IPR-PCI/MT32

• Software Application: IP CORE, Interface And Protocols, PCI
• Supported Families: Arria GX, Arria II GX, Cyclone, Stratix
• Core Architecture: FPGA
• Core Sub-architecture: Arria, Cyclone, Stratix
• Rohs Compliant: NA
• Function: PCI Compiler, Master/Target, 32 bit
• License: Renewal License
• Lead Free Status / RoHS Status: na
• Lead Free Status / RoHS Status: na

Altera Corporation
January 2011
req64n
irdyn
devseln
ack64n
trdyn
stopn
perrn
serrn
Table 3–2. PCI Interface Signals (Part 3 of 4)
Name
(1)
(1)
(1)
(1)
(1)
(1)
STS
STS
STS
STS
STS
STS
STS
Open-Drain Low
Type
Low
Low
Low
Low
Low
Low
Low
Polarity
PCI Compiler Version 10.1
Request 64-bit transfer. The
the current bus master and indicates that the master is
requesting a 64-bit transaction.
as
pci_t32
Initiator ready. The
to its target and indicates that the bus master can complete the
current data transaction. In a write transaction,
indicates that the address bus has valid data. In a read
transaction,
data.
Device select. Target asserts
target has decoded its own address and accepts the
transaction.
Acknowledge 64-bit transfer. The target asserts
indicate that the target can transfer data using 64 bits. The
ack64n
implemented in
Target ready. The
that the target can complete the current data transaction. In a
read operation,
valid data on the address bus. In a write operation,
indicates that the target is ready to accept data.
Stop. The
to the bus master to terminate the current transaction. The
stopn
to indicate the type of termination initiated by the target.
Parity error. The
perrn
par64
a parity error. The PCI MegaCore functions assert the
signal if a parity error is detected on the
and the
The
in
pci_t32
System error. The
address parity error. The PCI MegaCore functions assert
serrn
the
set.
pci_mt64
framen
serrn_ena
par64
signal is used in conjunction with
signal is asserted one clock cycle following the
if a parity error is detected during an address phase and
signals or two clock cycles following a data phase with
perrn_ena
has the same timing as
.
stopn
, only
. This signal is not implemented in
irdyn
signal is only evaluated during 64-bit transactions
and
trdyn
pci_mt32
par
perrn
enable bit (bit 8) in the command register is
signal is a target device request that indicates
trdyn
serrn
irdyn
pci_t64
indicates that the master is ready to accept
is evaluated.
bit (bit 6) in the command register is set.
indicates that the target is providing
signal indicates a data parity error. The
Description
signal is a target output, indicating
signal is an output from a bus master
signal indicates system error and
and
req64n
devseln
functions. In
req64n
pci_t32
devseln
signal is an output from
Functional Description
par
trdyn
to indicate that the
has the same timing
pci_mt32
.
. This signal is not
or
pci_mt32
irdyn
par64
and
ack64n
trdyn
devseln
par
perrn
and
signals
to
3–13
and
and