IPR-PCI/MT32 Altera, IPR-PCI/MT32 Datasheet - Page 40

• Manufacturer Part Number: IPR-PCI/MT32
• Description: IP CORE Renewal Of IP-PCI/MT32
• Manufacturer: Altera
• Type: MegaCorer

Specifications of IPR-PCI/MT32

• Software Application: IP CORE, Interface And Protocols, PCI
• Supported Families: Arria GX, Arria II GX, Cyclone, Stratix
• Core Architecture: FPGA
• Core Sub-architecture: Arria, Cyclone, Stratix
• Rohs Compliant: NA
• Function: PCI Compiler, Master/Target, 32 bit
• License: Renewal License
• Lead Free Status / RoHS Status: na
• Lead Free Status / RoHS Status: na

PCI MegaCore Function Design Walkthrough
1–6
PCI Compiler User Guide
4.
5.
6.
Click Next to open the Base Address Registers (BARs) page. This
page allows you to configure the PCI base address registers (BARs)
that define the address ranges of Memory and I/O write and read
requests that your application will claim for the PCI interface.
For this walkthrough, specify these settings:
a.
b.
c.
d.
e.
f.
g.
h.
i.
j.
k.
l.
m. Click OK.
Click Next to open the Advanced PCI MegaCore Features page. For
this walkthrough, use the default settings for all options on this
page.
Click Finish to complete the parameterization of your pci_mt64
MegaCore function variation.
Ensure that Implement Only 32 Bit BARs is selected under
32/64 Bit BARs.
Click BAR0 = 1 MBytes (Memory).
A window showing default settings for BAR0 displays. For this
walkthrough, use the default sliding pointer setting so that
BAR0 reserves 1 MByte (0xFFF00000) of memory.
Click OK.
Click BAR1 .
A window showing the default settings for BAR1 displays.
Turn on Enable.
Select I/O for the type of memory reserved.
Move the sliding pointer so that BAR1 reserves 64 Bytes
(0xFFFFFFC1) of I/O memory.
Click OK.
Select BAR2 Unused: Click to Configure.
A window showing default settings of BAR2 displays. Turn on
Enable.
Move the sliding pointer so that BAR2 reserves 1 MByte
(0xFFF00000) of memory.
PCI Compiler Version 10.1
Altera Corporation
January 2011