S1D13706F00A200 Epson, S1D13706F00A200 Datasheet - Page 99

• Manufacturer Part Number: S1D13706F00A200
• Description: LCD Drivers (QVGA) 320x240 LCD Controller @ 8bpp
• Manufacturer: Epson

Specifications of S1D13706F00A200

• Maximum Clock Frequency: 33 MHz
• Operating Supply Voltage: 1.8 V to 2.2 V, 3 V to 3.6 V
• Maximum Operating Temperature: + 85 C
• Package / Case: TQFP-100
• Attached Touch Screen: No
• Minimum Operating Temperature: - 40 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Epson Research and Development
Vancouver Design Center
bits 6-0
bits 9-0
Hardware Functional Specification
Issue Date: 2008/12/16
Horizontal Display Period Register
REG[14h]
Horizontal Display Period Start Position Register 0
REG[16h]
Horizontal Display Period Start Position Register 1
REG[17h]
n/a
7
7
7
6
6
6
Note
Note
For panel AC timing and timing parameter definitions, see Section 6.4, “Display Interface”
on page 52.
Horizontal Display Period Bits [6:0]
These bits specify the LCD panel Horizontal Display Period (HDP), in 8 pixel resolution.
The Horizontal Display Period should be less than the Horizontal Total to allow for a suf-
ficient Horizontal Non-Display Period.
Horizontal Display Period in number of pixels = ((REG[14h] bits 6:0) + 1) × 8
Horizontal Display Period Start Position Bits [9:0]
These bits specify a value used in the calculation of the Horizontal Display Period Start
Position (in 1 pixel resolution) for TFT, HR-TFT and D-TFD panels.
For passive LCD panels these bits must be set to 00h which will result in HDPS = 22.
For TFT/HR-TFT/D-TFD panels, HDPS is calculated using the following formula.
For further information on calculating the HDPS, see the specific panel AC Timing in Sec-
tion 6.4, “Display Interface” on page 52.
For passive panels, HDP must be a minimum of 32 pixels and can be increased by mul-
tiples of 16. For TFT panels, HDP must be a minimum of 16 pixels and can be increased
by multiples of 8.
This register must be programmed such that the following formula is valid.
HDPS + HDP < HT
HDPS = (REG[17h] bits 1-0, REG[16h] bits 7-0) + 22
HDPS = (REG[17h] bits 1-0, REG[16h] bits 7-0) + 5
5
5
5
Horizontal Display Period Start Position Bits 7-0
n/a
Horizontal Display Period Bits 6-0
4
4
4
Revision 10.3
3
3
3
2
2
2
Horizontal Display Period
Start Position Bits 9-8
1
1
1
Read/Write
Read/Write
Read/Write
X31B-A-001-10
S1D13706
0
0
0
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