S1D13706F00A200 Epson, S1D13706F00A200 Datasheet - Page 121

• Manufacturer Part Number: S1D13706F00A200
• Description: LCD Drivers (QVGA) 320x240 LCD Controller @ 8bpp
• Manufacturer: Epson

Specifications of S1D13706F00A200

• Maximum Clock Frequency: 33 MHz
• Operating Supply Voltage: 1.8 V to 2.2 V, 3 V to 3.6 V
• Maximum Operating Temperature: + 85 C
• Package / Case: TQFP-100
• Attached Touch Screen: No
• Minimum Operating Temperature: - 40 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Epson Research and Development
Vancouver Design Center
bit 3
bit 2
bit 1
Hardware Functional Specification
Issue Date: 2008/12/16
GPIO3 Pin IO Status
When neither a D-TFD panel or a HR-TFT are selected (REG[10h] bits 1:0) and GPIO3 is
configured as an output, writing a 1 to this bit drives GPIO3 high and writing a 0 to this bit
drives GPIO3 low.
When neither a D-TFD panel or a HR-TFT are selected (REG[10h] bits 1:0) and GPIO3 is
configured as an input, a read from this bit returns the status of GPIO3.
When a D-TFD panel is enabled (REG[10h] bits 1:0 = 11), GPIO3 outputs the FRS signal
automatically and writing to this bit has no effect.
When a HR-TFT panel is enabled (REG[10h] bits 1:0 = 10), GPIO3 outputs the SPL sig-
nal automatically and writing to this bit has no effect.
GPIO2 Pin IO Status
When neither a D-TFD panel or a HR-TFT are selected (REG[10h] bits 1:0) and GPIO2 is
configured as an output, writing a 1 to this bit drives GPIO2 high and writing a 0 to this bit
drives GPIO2 low.
When neither a D-TFD panel or a HR-TFT are selected (REG[10h] bits 1:0) and GPIO2 is
configured as an input, a read from this bit returns the status of GPIO2.
When a D-TFD panel is enabled (REG[10h] bits 1:0 = 11), GPIO2 outputs the FR signal
automatically and writing to this bit has no effect.
When a HR-TFT panel is enabled (REG[10h] bits 1:0 = 10), GPIO2 outputs the REV sig-
nal automatically and writing to this bit has no effect.
GPIO1 Pin IO Status
When neither a D-TFD panel or a HR-TFT are selected (REG[10h] bits 1:0) and GPIO1 is
configured as an output, writing a 1 to this bit drives GPIO1 high and writing a 0 to this bit
drives GPIO1 low.
When neither a D-TFD panel or a HR-TFT are selected (REG[10h] bits 1:0) and GPIO1 is
configured as an input, a read from this bit returns the status of GPIO1.
When a D-TFD panel is enabled (REG[10h] bits 1:0 = 11), GPIO1 outputs the YSCL sig-
nal automatically and writing to this bit has no effect.
When a HR-TFT panel is enabled (REG[10h] bits 1:0 = 10), GPIO1 outputs the CLS sig-
nal automatically and writing to this bit has no effect.
Revision 10.3
X31B-A-001-10
S1D13706
Page 121