S1D13706F00A200 Epson, S1D13706F00A200 Datasheet - Page 22

• Manufacturer Part Number: S1D13706F00A200
• Description: LCD Drivers (QVGA) 320x240 LCD Controller @ 8bpp
• Manufacturer: Epson

Specifications of S1D13706F00A200

• Maximum Clock Frequency: 33 MHz
• Operating Supply Voltage: 1.8 V to 2.2 V, 3 V to 3.6 V
• Maximum Operating Temperature: + 85 C
• Package / Case: TQFP-100
• Attached Touch Screen: No
• Minimum Operating Temperature: - 40 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Page 22
4.3.2 LCD Interface
S1D13706
X31B-A-001-10
FPDAT[17:0]
FPFRAME
Pin Name
FPSHIFT
FPLINE
GPIO0
GPIO1
DRDY
Type Pin #
IO
IO
O
O
O
O
O
74-64,
61-55
52
53
54
48
45
44
LB3M
LB3M
LB3P
LB3P
LB3P
LB3P
Cell
LO3
Table 4-3: LCD Interface Pin Descriptions
NIOVDD
NIOVDD
NIOVDD
NIOVDD
NIOVDD
NIOVDD
NIOVDD
Voltage
IO
RESET#
State
0
0
0
0
0
0
0
Revision 10.3
Panel Data bits 17-0.
This output pin has multiple functions.
See Table 4-9: “LCD Interface Pin Mapping,” on page 27 for
summary.
This output pin has multiple functions.
See Table 4-9: “LCD Interface Pin Mapping,” on page 27 for
summary.
This output pin has multiple functions.
See Table 4-9: “LCD Interface Pin Mapping,” on page 27 for
summary.
This output pin has multiple functions.
See Table 4-9: “LCD Interface Pin Mapping,” on page 27 for
summary.
This pin has multiple functions.
See Table 4-9: “LCD Interface Pin Mapping,” on page 27 for
summary.
This pin has multiple functions.
See Table 4-9: “LCD Interface Pin Mapping,” on page 27 for
summary.
• Frame Pulse
• SPS for Sharp HR-TFT
• DY for Epson D-TFD
• Line Pulse
• LP for Sharp HR-TFT
• LP for Epson D-TFD
• Shift Clock
• CLK for Sharp HR-TFT
• XSCL for Epson D-TFD
• Display enable (DRDY) for TFT panels
• 2nd shift clock (FPSHIFT2) for passive LCD with Format 1
• GCP for Epson D-TFD
• LCD backplane bias signal (MOD) for all other LCD panels
• PS for Sharp HR-TFT
• XINH for Epson D-TFD
• General purpose IO pin 0 (GPIO0)
• Hardware Video Invert
• CLS for Sharp HR-TFT
• YSCL for Epson D-TFD
• General purpose IO pin 1 (GPIO1)
interface
Description
Epson Research and Development
Hardware Functional Specification
Vancouver Design Center
Issue Date: 2008/12/16