S1D13706F00A200 Epson, S1D13706F00A200 Datasheet - Page 102

• Manufacturer Part Number: S1D13706F00A200
• Description: LCD Drivers (QVGA) 320x240 LCD Controller @ 8bpp
• Manufacturer: Epson

Specifications of S1D13706F00A200

• Maximum Clock Frequency: 33 MHz
• Operating Supply Voltage: 1.8 V to 2.2 V, 3 V to 3.6 V
• Maximum Operating Temperature: + 85 C
• Package / Case: TQFP-100
• Attached Touch Screen: No
• Minimum Operating Temperature: - 40 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Page 102
bits 9-0
bit 7
bits 2-0
S1D13706
X31B-A-001-10
FPLINE Pulse Start Position Register 0
REG[22h]
FPLINE Pulse Start Position Register 1
REG[23h]
FPFRAME Pulse Width Register
REG[24h]
Pulse Polarity
FPFRAME
7
7
7
6
6
6
Note
Note
Note
FPLINE Pulse Start Position in pixels = (REG[23h] bits 1-0, REG[22h] bits 7-0) + 1
FPLINE Pulse Start Position Bits [9:0]
These bits specify the start position of the horizontal sync signal, in 1 pixel resolution.
FPFRAME Pulse Polarity
This bit selects the polarity of the vertical sync signal. For passive panels, this bit must be
set to 1. For TFT panels, this bit is set according to the horizontal sync signal of the panel
(typically FPFRAME, SPS or DY).
When this bit = 0, the vertical sync signal is active low.
When this bit = 1, the vertical sync signal is active high.
FPFRAME Pulse Width Bits [2:0]
These bits specify the width of the panel vertical sync signal, in 1 line resolution. The ver-
tical sync signal is typically FPFRAME, SPS or DY, depending on the panel type.
FPFRAME Pulse Width in number of lines = (REG[24h] bits 2:0) + 1
For passive panels, these bits must be programmed such that the following formula is
valid.
For panel AC timing and timing parameter definitions, see Section 6.4, “Display Inter-
face” on page 52.
For panel AC timing and timing parameter definitions, see Section 6.4, “Display Inter-
face” on page 52.
HPW + HPS < HT
5
5
5
FPLINE Pulse Start Position Bits 7-0
n/a
n/a
4
4
4
Revision 10.3
3
3
3
2
2
2
FPFRAME Pulse Width Bits 2-0
Epson Research and Development
Hardware Functional Specification
FPLINE Pulse Start Position
1
1
1
Vancouver Design Center
Issue Date: 2008/12/16
Bits 9-8
Read/Write
Read/Write
Read/Write
0
0
0