S1D13706F00A200 Epson, S1D13706F00A200 Datasheet - Page 54

• Manufacturer Part Number: S1D13706F00A200
• Description: LCD Drivers (QVGA) 320x240 LCD Controller @ 8bpp
• Manufacturer: Epson

Specifications of S1D13706F00A200

• Maximum Clock Frequency: 33 MHz
• Operating Supply Voltage: 1.8 V to 2.2 V, 3 V to 3.6 V
• Maximum Operating Temperature: + 85 C
• Package / Case: TQFP-100
• Attached Touch Screen: No
• Minimum Operating Temperature: - 40 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Page 54
VT
VPS
VPW
VDPS
VDP
HT
HPS
HPW
HDPS
HDP
*For passive panels, the HDP must be a minimum of 32 pixels and must be increased by multiples of 16.
*HPS must comply with the following formula:
*Panel Type Bits (REG[10h] bits 1-0) = 00b (STN)
*FPFRAME Pulse Polarity Bit (REG[24h] bit 7) = 1 (active high)
*FPLINE Polarity Bit (REG[20h] bit 7) = 1 (active high)
*MOD
*MOD
S1D13706
X31B-A-001-10
1
2
is the MOD signal when (REG[11h] bits 5-0) = 0 (MOD toggles every FPFRAME)
is the MOD signal when (REG[11h] bits 5-0) = n (MOD toggles every n FPLINE)
= Vertical Total
= [(REG[19h] bits 1-0, REG[18h] bits 7-0) + 1] lines
= FPFRAME Pulse Start Position
= 0 lines, because (REG[27h] bits 1-0, REG[26h] bits 7-0) = 0
= FPFRAME Pulse Width
= [(REG[24h] bits 2-0) + 1] lines
= Vertical Display Period Start Position
= 0 lines, because (REG[1Fh] bits 1-0, REG[1Eh] bits 7-0) = 0
= Vertical Display Period
= [(REG[1Dh] bits 1-0, REG[1Ch] bits 7-0) + 1] lines
= Horizontal Total
= [((REG[12h] bits 6-0) + 1) x 8] pixels
= FPLINE Pulse Start Position
= [(REG[23h] bits 1-0, REG[22h] bits 7-0) + 1] pixels
= FPLINE Pulse Width
= [(REG[20h] bits 6-0) + 1] pixels
= Horizontal Display Period Start Position
= 22 pixels, because (REG[17h] bits 1-0, REG[16h] bits 7-0) = 0
= Horizontal Display Period
= [((REG[14h] bits 6-0) + 1) x 8] pixels
HPS > HDP + 22
HPS + HPW < HT
Revision 10.3
Epson Research and Development
Hardware Functional Specification
Vancouver Design Center
Issue Date: 2008/12/16