S1D13706F00A200 Epson, S1D13706F00A200 Datasheet - Page 98

• Manufacturer Part Number: S1D13706F00A200
• Description: LCD Drivers (QVGA) 320x240 LCD Controller @ 8bpp
• Manufacturer: Epson

Specifications of S1D13706F00A200

• Maximum Clock Frequency: 33 MHz
• Operating Supply Voltage: 1.8 V to 2.2 V, 3 V to 3.6 V
• Maximum Operating Temperature: + 85 C
• Package / Case: TQFP-100
• Attached Touch Screen: No
• Minimum Operating Temperature: - 40 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

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bits 1-0
bits 5-0
bits 6-0
S1D13706
X31B-A-001-10
MOD Rate Register
REG[11h]
Horizontal Total Register
REG[12h]
n/a
7
7
n/a
6
6
Note
Panel Type Bits[1:0]
These bits select the panel type.
MOD Rate Bits [5:0]
These bits are for passive LCD panels only.
When these bits are all 0, the MOD output signal (DRDY) toggles every FPFRAME.
For a non-zero value n, the MOD output signal (DRDY) toggles every n FPLINE.
Horizontal Total Bits [6:0]
These bits specify the LCD panel Horizontal Total period, in 8 pixel resolution. The Hori-
zontal Total is the sum of the Horizontal Display period and the Horizontal Non-Display
period. Since the maximum Horizontal Total is 1024 pixels, the maximum panel resolu-
tion supported is 800x600.
Horizontal Total in number of pixels = ((REG[12h] bits 6:0) + 1) × 8
1
2
face” on page 52.
This register must be programmed such that the following formulas are valid.
For panel AC timing and timing parameter definitions, see Section 6.4, “Display Inter-
HDPS + HDP < HT
REG[10h] Bits[1:0]
5
5
Table 8-7: LCD Panel Type Selection
00
01
10
11
4
4
Revision 10.3
Horizontal Total Bits 6-0
MOD Rate Bits 5-0
3
3
Panel Type
HR-TFT
D-TFD
STN
TFT
2
2
Epson Research and Development
Hardware Functional Specification
1
1
Vancouver Design Center
Issue Date: 2008/12/16
Read/Write
Read/Write
0
0