S1D13706F00A200 Epson, S1D13706F00A200 Datasheet - Page 125

• Manufacturer Part Number: S1D13706F00A200
• Description: LCD Drivers (QVGA) 320x240 LCD Controller @ 8bpp
• Manufacturer: Epson

Specifications of S1D13706F00A200

• Maximum Clock Frequency: 33 MHz
• Operating Supply Voltage: 1.8 V to 2.2 V, 3 V to 3.6 V
• Maximum Operating Temperature: + 85 C
• Package / Case: TQFP-100
• Attached Touch Screen: No
• Minimum Operating Temperature: - 40 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Epson Research and Development
Vancouver Design Center
bits 7-4
bits 3-1
bit 0
Hardware Functional Specification
Issue Date: 2008/12/16
PWM Clock / CV Pulse Configuration Register
REG[B1h]
7
PWM Clock Divide Select Bits 3-0
PWM Clock Divide Select Bits [3:0]
CV Pulse Divide Select Bits [2:0]
6
Note
Note
Note
PWM Clock Divide Select Bits [3:0]
The value of these bits represents the power of 2 by which the selected PWM clock source
is divided.
CV Pulse Divide Select Bits [2:0]
The value of these bits represents the power of 2 by which the selected CV Pulse source is
divided.
PWMCLK Source Select
When this bit = 0, the clock source for PWMCLK is CLKI.
When this bit = 1, the clock source for PWMCLK is CLKI2.
This divided clock is further divided by 256 before it is output at PWMOUT.
This divided clock is further divided by 2 before it is output at the CVOUT.
For further information on the PWMCLK source select, see Section 7.2, “Clock Selec-
tion” on page 87.
Dh-Fh
Ch
0h
1h
2h
3h
0h
1h
2h
3h
7h
...
...
Table 8-17: PWM Clock Divide Select Options
Table 8-18: CV Pulse Divide Select Options
5
4
Revision 10.3
3
CV Pulse Divide Select Bits 2-0
PWM Clock Divide Amount
CV Pulse Divide Amount
Reserved
4096
2
128
...
...
1
2
4
8
1
2
4
8
1
Source Select
Read/Write
X31B-A-001-10
PWMCLK
S1D13706
0
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