S1D13706F00A200 Epson, S1D13706F00A200 Datasheet - Page 85

• Manufacturer Part Number: S1D13706F00A200
• Description: LCD Drivers (QVGA) 320x240 LCD Controller @ 8bpp
• Manufacturer: Epson

Specifications of S1D13706F00A200

• Maximum Clock Frequency: 33 MHz
• Operating Supply Voltage: 1.8 V to 2.2 V, 3 V to 3.6 V
• Maximum Operating Temperature: + 85 C
• Package / Case: TQFP-100
• Attached Touch Screen: No
• Minimum Operating Temperature: - 40 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Epson Research and Development
Vancouver Design Center
7.1.3 PCLK
Hardware Functional Specification
Issue Date: 2008/12/16
PCLK is the internal clock used to control the LCD panel. PCLK should be chosen to match
the optimum frame rate of the LCD panel. See Section 9, “Frame Rate Calculation” on page
127 for details on the relationship between PCLK and frame rate.
Some flexibility is possible in the selection of PCLK. Firstly, LCD panels typically have a
range of permissible frame rates. Secondly, it may be possible to choose a higher PCLK
frequency and tailor the horizontal and vertical non-display periods to lower the frame-rate
to its optimal value.
The source clock options for PCLK may be selected as in the following table.
Source Clock Options
Revision 10.3
MCLK
MCLK
MCLK
MCLK
CLKI2
CLKI2
CLKI2
CLKI2
BCLK
BCLK
BCLK
BCLK
CLKI
CLKI
CLKI
CLKI
Table 7-3: PCLK Clock Selection
MCLK
CLKI2
BCLK
CLKI
÷
÷
÷
÷
÷
÷
÷
÷
÷
÷
÷
÷
÷
÷
÷
÷
2
3
4
8
2
3
4
8
2
3
4
8
2
3
4
8
PCLK Selection
REG[05h] = 00h
REG[05h] = 10h
REG[05h] = 20h
REG[05h] = 30h
REG[05h] = 40h
REG[05h] = 01h
REG[05h] = 11h
REG[05h] = 21h
REG[05h] = 31h
REG[05h] = 41h
REG[05h] = 02h
REG[05h] = 12h
REG[05h] = 22h
REG[05h] = 32h
REG[05h] = 42h
REG[05h] = 03h
REG[05h] = 13h
REG[05h] = 23h
REG[05h] = 33h
REG[05h] = 43h
X31B-A-001-10
S1D13706
Page 85