S1D13706F00A200 Epson, S1D13706F00A200 Datasheet - Page 27

• Manufacturer Part Number: S1D13706F00A200
• Description: LCD Drivers (QVGA) 320x240 LCD Controller @ 8bpp
• Manufacturer: Epson

Specifications of S1D13706F00A200

• Maximum Clock Frequency: 33 MHz
• Operating Supply Voltage: 1.8 V to 2.2 V, 3 V to 3.6 V
• Maximum Operating Temperature: + 85 C
• Package / Case: TQFP-100
• Attached Touch Screen: No
• Minimum Operating Temperature: - 40 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Epson Research and Development
Vancouver Design Center
4.6 LCD Interface Pin Mapping
Hardware Functional Specification
Issue Date: 2008/12/16
FPFRAME
Pin Name
PWMOUT
FPDAT10
FPDAT11
FPDAT12
FPDAT13
FPDAT14
FPDAT15
FPDAT16
FPDAT17
FPSHIFT
FPDAT0
FPDAT1
FPDAT2
FPDAT3
FPDAT4
FPDAT5
FPDAT6
FPDAT7
FPDAT8
FPDAT9
FPLINE
CVOUT
GPIO0
GPIO1
GPIO2
GPIO3
GPIO4
GPIO5
GPIO6
DRDY
GPO
Monochrome Passive
driven 0
driven 0
driven 0
driven 0
driven 0
driven 0
driven 0
driven 0
driven 0
driven 0
driven 0
driven 0
driven 0
driven 0
GPIO0
GPIO1
GPIO2
GPIO3
GPIO4
GPIO5
GPIO6
4-bit
D0
D1
D2
D3
Single
Panel
driven 0
driven 0
driven 0
driven 0
driven 0
driven 0
driven 0
driven 0
driven 0
driven 0
GPIO0
GPIO1
GPIO2
GPIO3
GPIO4
GPIO5
GPIO6
MOD
8-bit
D0
D1
D2
D3
D4
D5
D6
D7
Note
2
3
1
GPIO pins must be configured as outputs (CNF3 = 0 at RESET#) when the HR-TFT or
These pin mappings use signal names commonly used for each panel type, however
When the HR-TFT interface is selected (REG[10h] bits 1-0 = 10), this GPO can be
D-TFD interface is selected.
signal names may differ between panel manufacturers. The values shown in brackets
represent the color components as mapped to the corresponding FPDATxx signals at
the first valid edge of FPSHIFT. For further FPDATxx to LCD interface mapping, see
Section 6.4, “Display Interface” on page 52.
used to control the HR-TFT MOD signal. Note this is not the same signal as the
S1D13706 DRDY(MOD) signal used for passive panels.
D0 (R2)
D1 (B1)
D2 (G1)
D3 (R1)
driven 0
driven 0
driven 0
driven 0
driven 0
driven 0
driven 0
driven 0
driven 0
driven 0
driven 0
driven 0
driven 0
driven 0
GPIO0
GPIO1
GPIO2
GPIO3
GPIO4
GPIO5
GPIO6
4-bit
2
2
2
2
Table 4-9: LCD Interface Pin Mapping
FPSHIFT2
Format 1
D2 (G4)
D5 (G2)
D0 (B5)
D1 (R5)
D3 (B3)
D4 (R3)
D6 (B1)
D7 (R1)
driven 0
driven 0
driven 0
driven 0
driven 0
driven 0
driven 0
driven 0
driven 0
driven 0
Color Passive Panel
GPIO0
GPIO1
GPIO2
GPIO3
GPIO4
GPIO5
GPIO6
8-bit
GPO (General Purpose Output)
2
2
2
2
2
2
2
2
Single
FPFRAME
FPSHIFT
FPLINE
Format 2
D0 (G3)
D1 (R3)
D3 (G2)
D4 (R2)
D6 (G1)
D7 (R1)
D2 (B2)
D5 (B1)
driven 0
driven 0
driven 0
driven 0
driven 0
driven 0
driven 0
driven 0
driven 0
driven 0
Revision 10.3
GPIO0
GPIO1
GPIO2
GPIO3
GPIO4
GPIO5
GPIO6
8-bit
2
2
2
2
2
2
2
2
MOD
PWMOUT
D10 (G4)
D13 (G2)
D11 (B3)
D12 (R3)
D14 (B1)
D15 (R1)
CVOUT
D0 (R6)
D1 (G5)
D2 (B4)
D3 (R4)
D8 (B5)
D9 (R5)
D4 (G3)
D5 (B2)
D6 (R2)
D7 (G1)
driven 0
driven 0
GPIO0
GPIO1
GPIO2
GPIO3
GPIO4
GPIO5
GPIO6
16-Bit
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
driven 0
driven 0
driven 0
driven 0
driven 0
driven 0
driven 0
driven 0
driven 0
GPIO0
GPIO1
GPIO2
GPIO3
GPIO4
GPIO5
GPIO6
9-bit
R2
R1
R0
G2
G1
G0
B2
B1
B0
driven 0
driven 0
driven 0
driven 0
driven 0
driven 0
Others
GPIO0
GPIO1
GPIO2
GPIO3
GPIO4
GPIO5
GPIO6
DRDY
12-bit
R3
R2
R1
G3
G2
G1
B3
B2
B1
R0
G0
B0
Color TFT Panel
GPIO0
GPIO1
GPIO2
GPIO3
GPIO4
GPIO5
GPIO6
18-bit
R5
R4
R3
G5
G4
G3
B5
B4
B3
R2
R1
R0
G2
G1
G0
B2
B1
B0
(output only)
(output only)
(output only)
Sharp HR-
no connect
GPIO4
GPIO5
GPIO6
18-bit
DCLK
MOD
TFT
SPS
REV
CLS
SPL
G5
G4
G3
G2
G1
G0
PS
LP
R5
R4
R3
B5
B4
B3
R2
R1
R0
B2
B1
B0
X31B-A-001-10
1
3
S1D13706
Page 27
D-TFD
YSCLD
DD_P1
Epson
18-bit
XSCL
YSCL
XINH
GCP
GPO
FRS
RES
DY
LP
R5
R4
R3
G5
G4
G3
B5
B4
B3
R2
R1
R0
G2
G1
G0
B2
B1
B0
FR
1