S1D13706F00A200 Epson, S1D13706F00A200 Datasheet - Page 123

LCD Drivers (QVGA) 320x240 LCD Controller @ 8bpp

S1D13706F00A200

Manufacturer Part Number
S1D13706F00A200
Description
LCD Drivers (QVGA) 320x240 LCD Controller @ 8bpp
Manufacturer
Epson
Datasheet

Specifications of S1D13706F00A200

Maximum Clock Frequency
33 MHz
Operating Supply Voltage
1.8 V to 2.2 V, 3 V to 3.6 V
Maximum Operating Temperature
+ 85 C
Package / Case
TQFP-100
Attached Touch Screen
No
Minimum Operating Temperature
- 40 C
Lead Free Status / RoHS Status
Lead free / RoHS Compliant

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
S1D13706F00A200
Manufacturer:
Epson Electronics America Inc-Semiconductor Div
Quantity:
10 000
Epson Research and Development
Vancouver Design Center
8.3.9 Pulse Width Modulation (PWM) Clock and Contrast Voltage (CV) Pulse
Configuration Registers
bit 7 and bit 4
Hardware Functional Specification
Issue Date: 2008/12/16
PWM Clock / CV Pulse Control Register
REG[B0h]
PWM Clock
Force High
PWMCLK
7
x = don’t care
Bit 7
0
0
1
m = PWM Clock Divide Select value
x = CV Pulse Divide Select value
6
Note
Note
PWM Clock Force High (bit 7) and PWM Clock Enable (bit 4)
These bits control the PWMOUT pin and PWM Clock circuitry as follows.
When PWMOUT is forced low or forced high it can be used as a general purpose output.
Clock Source / 2
Clock Source / 2
PWM Clock
Divider
For further information on PWMCLK, see Section 7.1.4, “PWMCLK” on page 86.
The PWM Clock circuitry is disabled when Power Save Mode is enabled.
CV Pulse
Divider
n/a
Figure 8-2: PWM Clock/CV Pulse Block Diagram
5
Bit 4
1
0
x
m
x
Table 8-15: PWM Clock Control
Divided
Clock
PWM Clock
Divided
Clock
Enable
4
Revision 10.3
PWM Clock Force High
PWM Duty Cycle
Modulation
y = Burst Length value
CV Pulse Burst
Generation
CV Pulse Enable
CV Pulse Force High
Duty = n / 256
n = PWM Clock Duty Cycle
PWM Clock Enable
y-pulse burst
Force High
CV Pulse
(controlled by REG[B1h] and REG[B3h])
3
PWM Clock circuitry enabled
PWMOUT forced high
PWMOUT forced low
Burst Status
CV Pulse
(RO)
2
Result
Burst Start
CV Pulse
Clock Source / (2
frequency =
Clock Source / (2
frequency =
1
to PWMOUT
Read/Write
to CVOUT
X31B-A-001-10
CV Pulse
Enable
m
x
S1D13706
X 256)
0
Page 123
X 2)

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