S1D13706F00A200 Epson, S1D13706F00A200 Datasheet - Page 67

• Manufacturer Part Number: S1D13706F00A200
• Description: LCD Drivers (QVGA) 320x240 LCD Controller @ 8bpp
• Manufacturer: Epson

Specifications of S1D13706F00A200

• Maximum Clock Frequency: 33 MHz
• Operating Supply Voltage: 1.8 V to 2.2 V, 3 V to 3.6 V
• Maximum Operating Temperature: + 85 C
• Package / Case: TQFP-100
• Attached Touch Screen: No
• Minimum Operating Temperature: - 40 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Epson Research and Development
Vancouver Design Center
6.4.8 Generic TFT Panel Timing
VT
VPS
VPW
VDPS
VDP
HT
HPS
HPW
HDPS
HDP
*For TFT panels, the HDP must be a minimum of 8 pixels and must be increased by multiples of 8.
*Panel Type Bits (REG[10h] bits 1-0) = 01 (TFT)
*FPLINE Pulse Polarity Bit (REG[24h] bit 7) = 0 (active low)
*FPFRAME Polarity Bit (REG[20h] bit 7) = 0 (active low)
Hardware Functional Specification
Issue Date: 2008/12/16
FPDAT[17:0]
FPDAT[17:0]
FPFRAME
FPLINE
DRDY
FPLINE
FPSHIFT
= Vertical Total
= FPFRAME Pulse Start Position
= FPFRAME Pulse Width
= Vertical Display Period Start Position
= Vertical Display Period
= Horizontal Total
= FPLINE Pulse Start Position
= FPLINE Pulse Width
= Horizontal Display Period Start Position = [(REG[17h] bits 1-0, REG[16h] bits 7-0) + 5] pixels
= Horizontal Display Period
DRDY
VPS
HPS
invalid
HDPS
HPW
Figure 6-27: Generic TFT Panel Timing
VPW
VDPS
Revision 10.3
= [(REG[19h] bits 1-0, REG[18h] bits 7-0) + 1] lines
= (REG[27h] bits 1-0, REG[26h] bits 7-0) lines
= [(REG[24h] bits 2-0) + 1] lines
= (REG[1Fh] bits 1-0, REG[1Eh] bits 7-0) lines
= [(REG[1Dh] bits 1-0, REG[1Ch] bits 7-0) + 1] lines
= [((REG[12h] bits 6-0) + 1) x 8] pixels
= [(REG[23h] bits 1-0, REG[22h] bits 7-0) + 1] pixels
= [(REG[20h] bits 6-0) + 1] pixels
= [((REG[14h] bits 6-0) + 1) x 8] pixels
HT (= 1 Line)
HDP
VT (= 1 Frame)
VDP
invalid
X31B-A-001-10
S1D13706
Page 67