S1D13706F00A200 Epson, S1D13706F00A200 Datasheet - Page 52
S1D13706F00A200
Manufacturer Part Number
S1D13706F00A200
Description
LCD Drivers (QVGA) 320x240 LCD Controller @ 8bpp
Manufacturer
Epson
Datasheet
1.S1D13706F00A200.pdf
(150 pages)
Specifications of S1D13706F00A200
Maximum Clock Frequency
33 MHz
Operating Supply Voltage
1.8 V to 2.2 V, 3 V to 3.6 V
Maximum Operating Temperature
+ 85 C
Package / Case
TQFP-100
Attached Touch Screen
No
Minimum Operating Temperature
- 40 C
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
S1D13706F00A200
Manufacturer:
Epson Electronics America Inc-Semiconductor Div
Quantity:
10 000
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HT
HDP
HDPS
HPS
HPW
VT
VDP
VDPS
VPS
VPW
Page 52
6.4 Display Interface
Symbol
1. For passive panels, the HDP must be a minimum of 32 pixels and must be increased by multiples of 16.
2. The following formulas must be valid for all panel timings:
S1D13706
X31B-A-001-10
1
For TFT panels, the HDP must be a minimum of 8 pixels and must be increased by multiples of 8.
Horizontal Total
Horizontal Display Period
Horizontal Display Period Start Position
FPLINE Pulse Start Position
FPLINE Pulse Width
Vertical Total
Vertical Display Period
Vertical Display Period Start Position
FPFRAME Pulse Start Position
FPFRAME Pulse Width
VT
HDPS + HDP < HT
VDPS + VDP < VT
VDPS
Table 6-16: Panel Timing Parameter Definition and Register Summary
VPW
VPS
Description
The timing parameters required to drive a flat panel display are shown below. Timing
details for each supported panel type are provided in the remainder of this section.
HDPS
1
Figure 6-13: Panel Timing Parameters
HDP
VDP
((REG[12h] bits 6-0) + 1) x 8
((REG[14h] bits 6-0) + 1) x 8
For STN panels: ((REG[17h] bits 1-0, REG[16h] bits 7-0) + 22 )
For TFT panels: ((REG[17h] bits 1-0, REG[16h] bits 7-0) + 5 )
(REG[23h] bits 1-0, REG[22h] bits 7-0) + 1
(REG[20h] bits 6-0) + 1
(REG[19h] bits 1-0, REG[18h] bits 7-0) + 1
(REG[1Dh] bits 1-0, REG[1Ch] bits 7-0) + 1
REG[1Fh] bits 1-0, REG[1Eh] bits 7-0
REG[27h] bits 1-0, REG[26h] bits 7-0
(REG[24h] bits 6-0) + 1
HPS
Revision 10.3
HT
Derived From
HPW
Epson Research and Development
Hardware Functional Specification
Vancouver Design Center
Issue Date: 2008/12/16
Lines (HT)
Units
Ts
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