S1D13706F00A200 Epson, S1D13706F00A200 Datasheet - Page 33

• Manufacturer Part Number: S1D13706F00A200
• Description: LCD Drivers (QVGA) 320x240 LCD Controller @ 8bpp
• Manufacturer: Epson

Specifications of S1D13706F00A200

• Maximum Clock Frequency: 33 MHz
• Operating Supply Voltage: 1.8 V to 2.2 V, 3 V to 3.6 V
• Maximum Operating Temperature: + 85 C
• Package / Case: TQFP-100
• Attached Touch Screen: No
• Minimum Operating Temperature: - 40 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Epson Research and Development
Vancouver Design Center
1. t11 is the delay from when data is placed on the bus until the data is latched into the write buffer.
2. When WAIT# is used, the Host will assert RD0#, RD1#, WE0#, WE1# for up to 8.5T
3. When WAIT# is used, the Host will assert RD0#, RD1#, WE0#, WE1# for up to 11.5T
4. When WAIT# is used, the Host will assert RD0#, RD1#, WE0#, WE1# for up to 13.5T
5. When WAIT# is used, the Host will assert RD0#, RD1#, WE0#, WE1# for up to 17.5T
Hardware Functional Specification
Issue Date: 2008/12/16
Symbol
T
f
t7a
t7b
t7c
t7d
t10
t11
t12
t13
t14
t15
CLK
CLK
t1
t2
t3
t4
t5
t6
t8
t9
Bus Clock frequency
Bus Clock period
Clock pulse width high
Clock pulse width low
A[16:1], M/R# setup to first CLK rising edge where CS# = 0 and
either RD0#, RD1# = 0 or WE0#, WE1# = 0
A[16:1], M/R# hold from either RD0#, RD1# or WE0#, WE1#
rising edge
CS# setup to CLK rising edge
CS# hold from either RD0#, RD1# or WE0#, WE1# rising edge
RD0#, RD1#, WE0#, WE1# asserted for MCLK = BCLK when
WAIT# is not used (see Note 2)
RD0#, RD1#, WE0#, WE1# asserted for MCLK = BCLK
when WAIT# is not used (see Note 3)
RD0#, RD1#, WE0#, WE1# asserted for MCLK = BCLK
when WAIT# is not used (see Note 4)
RD0#, RD1#, WE0#, WE1# asserted for MCLK = BCLK
when WAIT# is not used (see Note 5)
RD0#, RD1#, WE0#, WE1# setup to CLK rising edge
Falling edge of either RD0#, RD1# or WE0#, WE1# to WAIT#
driven low
Rising edge of either RD0#, RD1# or WE0#, WE1# to WAIT#
high impedance
D[15:0] setup to third CLK rising edge where CS# = 0 and
WE0#, WE1# = 0 (write cycle) (see note 1)
D[15:0] hold from WAIT# rising edge (write cycle)
RD0#, RD1# falling edge to D[15:0] driven (read cycle)
WAIT# rising edge to D[15:0] valid (read cycle)
RD0#, RD1# rising edge to D[15:0] high impedance (read cycle)
Parameter
Table 6-5: Generic #1 Interface Timing
Revision 10.3
÷ 2
÷ 3
÷ 4
1/f
22.5
22.5
11.5
13.5
17.5
Min
8.5
1
0
0
0
2
5
5
1
1
4
3
CLK
2.0V
Max
20
31
34
27
29
0
1/f
CLK
11.5
13.5
17.5
Min
8.5
CLK
CLK
CLK
9
9
1
0
1
0
1
3
3
0
3
3
CLK
0
.
.
.
.
3.3V
Max
15
13
14
11
50
2
X31B-A-001-10
S1D13706
T
T
T
T
Unit
MHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Page 33
CLK
CLK
CLK
CLK