S1D13706F00A200 Epson, S1D13706F00A200 Datasheet - Page 124

• Manufacturer Part Number: S1D13706F00A200
• Description: LCD Drivers (QVGA) 320x240 LCD Controller @ 8bpp
• Manufacturer: Epson

Specifications of S1D13706F00A200

• Maximum Clock Frequency: 33 MHz
• Operating Supply Voltage: 1.8 V to 2.2 V, 3 V to 3.6 V
• Maximum Operating Temperature: + 85 C
• Package / Case: TQFP-100
• Attached Touch Screen: No
• Minimum Operating Temperature: - 40 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

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bit 3 and bit 0
bit 2
bit 1
bit 0
S1D13706
X31B-A-001-10
x = don’t care
Bit 3
0
0
1
Note
Note
CV Pulse Force High (bit 3) and CV Pulse Enable (bit 0)
These bits control the CVOUT pin and CV Pulse circuitry as follows.
When CVOUT is forced low or forced high it can be used as a general purpose output.
CV Pulse Burst Status
This is a read-only bit. A “1” indicates a CV pulse burst is occurring. A “0” indicates no
CV pulse burst is occurring. Software should wait for this bit to clear before starting
another burst.
CV Pulse Burst Start
A 1 in this bit initiates a single CVOUT pulse burst. The number of clock pulses generated
is programmable from 1 to 256. The frequency of the pulses is the divided CV Pulse
source divided by 2, with 50/50 duty cycle. This bit should be cleared to 0 by software
before initiating a new burst.
CV Pulse Enable
See description for bit 3.
1
CV Pulse Burst Start bit.
2
This bit has effect only if the CV Pulse Enable bit is 1.
Bit 3 must be set to 0 and bit 0 must be set to 1 before initiating a new burst using the
The CV Pulse circuitry is disabled when Power Save Mode is enabled.
Bit 0
1
0
x
Table 8-16: CV Pulse Control
Revision 10.3
(controlled by REG[B1h] and REG[B2h])
CV Pulse circuitry enabled
CVOUT forced high
CVOUT forced low
Result
Epson Research and Development
Hardware Functional Specification
Vancouver Design Center
Issue Date: 2008/12/16