S1D13706F00A200 Epson, S1D13706F00A200 Datasheet - Page 100

• Manufacturer Part Number: S1D13706F00A200
• Description: LCD Drivers (QVGA) 320x240 LCD Controller @ 8bpp
• Manufacturer: Epson

Specifications of S1D13706F00A200

• Maximum Clock Frequency: 33 MHz
• Operating Supply Voltage: 1.8 V to 2.2 V, 3 V to 3.6 V
• Maximum Operating Temperature: + 85 C
• Package / Case: TQFP-100
• Attached Touch Screen: No
• Minimum Operating Temperature: - 40 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Page 100
bits 9-0
bits 9-0
S1D13706
X31B-A-001-10
Vertical Total Register 0
REG[18h]
Vertical Total Register 1
REG[19h]
Vertical Display Period Register 0
REG[1Ch]
Vertical Display Period Register 1
REG[1Dh]
7
7
7
7
6
6
6
6
Note
Note
Vertical Total Bits [9:0]
These bits specify the LCD panel Vertical Total period, in 1 line resolution. The Vertical
Total is the sum of the Vertical Display Period and the Vertical Non-Display Period. The
maximum Vertical Total is 1024 lines.
Vertical Total in number of lines = (REG[18h] bits 7:0, REG[19h] bits 1:0) + 1
Vertical Display Period Bits [9:0]
These bits specify the LCD panel Vertical Display period, in 1 line resolution. The Vertical
Display period should be less than the Vertical Total to allow for a sufficient Vertical
Non-Display period.
Vertical Display Period in number of lines = (REG[1Ch] bits 7:0, REG[1Dh] bits 1:0) + 1
1
2
face” on page 52.
For panel AC timing and timing parameter definitions, see Section 6.4, “Display Inter-
face” on page 52.
This register must be programmed such that the following formula is valid.
For panel AC timing and timing parameter definitions, see Section 6.4, “Display Inter-
VDPS + VDP < VT
5
5
5
5
n/a
n/a
Vertical Display Period Bits 7-0
Vertical Total Bits 7-0
4
4
4
4
Revision 10.3
3
3
3
3
2
2
2
2
Epson Research and Development
Hardware Functional Specification
Vertical Display Period
Vertical Total Bits 9-8
1
1
1
1
Vancouver Design Center
Issue Date: 2008/12/16
Bits 9-8
Read/Write
Read/Write
Read/Write
Read/Write
0
0
0
0