S1D13706F00A200 Epson, S1D13706F00A200 Datasheet - Page 21

• Manufacturer Part Number: S1D13706F00A200
• Description: LCD Drivers (QVGA) 320x240 LCD Controller @ 8bpp
• Manufacturer: Epson

Specifications of S1D13706F00A200

• Maximum Clock Frequency: 33 MHz
• Operating Supply Voltage: 1.8 V to 2.2 V, 3 V to 3.6 V
• Maximum Operating Temperature: + 85 C
• Package / Case: TQFP-100
• Attached Touch Screen: No
• Minimum Operating Temperature: - 40 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Epson Research and Development
Vancouver Design Center
Hardware Functional Specification
Issue Date: 2008/12/16
Pin Name Type Pin #
RESET#
WAIT#
O
I
17
13
LB2A
Cell
LIS
HIOVDD
HIOVDD
Table 4-2: Host Interface Pin Descriptions
Voltage
IO
RESET#
State
Hi-Z
—
Revision 10.3
During a data transfer, this output pin is driven active to force the
system to insert wait states. It is driven inactive to indicate the
completion of a data transfer. WAIT# is released to the high
impedance state after the data transfer is complete. Its active
polarity is configurable. See Table 4-7: “Summary of Power-
On/Reset Options,” on page 25.
See Table 4-8: “Host Bus Interface Pin Mapping,” on page 26 for
summary.
Active low input to set all internal registers to the default state and
to force all signals to their inactive states.
• For Generic #1, this pin outputs the wait signal (WAIT#).
• For Generic #2, this pin outputs the wait signal (WAIT#).
• For SH-3 mode, this pin outputs the wait request signal
• For SH-4 mode, this pin outputs the device ready signal
• For MC68K #1, this pin outputs the data transfer acknowledge
• For MC68K #2, this pin outputs the data transfer and size
• For REDCAP2, this pin is unused (Hi-Z).
• For DragonBall, this pin outputs the data transfer
(WAIT#).
(RDY#).
signal (DTACK#).
acknowledge bit 1 (DSACK1#).
acknowledge signal (DTACK).
Description
X31B-A-001-10
S1D13706
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