S1D13706F00A200 Epson, S1D13706F00A200 Datasheet - Page 24

LCD Drivers (QVGA) 320x240 LCD Controller @ 8bpp

S1D13706F00A200

Manufacturer Part Number
S1D13706F00A200
Description
LCD Drivers (QVGA) 320x240 LCD Controller @ 8bpp
Manufacturer
Epson
Datasheet

Specifications of S1D13706F00A200

Maximum Clock Frequency
33 MHz
Operating Supply Voltage
1.8 V to 2.2 V, 3 V to 3.6 V
Maximum Operating Temperature
+ 85 C
Package / Case
TQFP-100
Attached Touch Screen
No
Minimum Operating Temperature
- 40 C
Lead Free Status / RoHS Status
Lead free / RoHS Compliant

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
S1D13706F00A200
Manufacturer:
Epson Electronics America Inc-Semiconductor Div
Quantity:
10 000
Page 24
4.3.3 Clock Input
4.3.4 Miscellaneous
4.3.5 Power And Ground
S1D13706
X31B-A-001-10
COREVDD
Pin Name Type Pin #
Pin Name Type Pin #
Pin Name Type Pin #
CNF[7:0]
TESTEN
HIOVDD
NIOVDD
CLKI2
CLKI
GPO
VSS
O
P
P
P
P
I
I
I
I
37, 49,
14, 25,
36, 50,
62, 75,
16, 26
63, 76
78-85
1, 51
100
15
77
47
86
Cell
Cell
LO3
Cell
T1
LI
LI
LI
P
P
P
P
Table 4-6: Power And Ground Pin Descriptions
NIOVDD
NIOVDD
NIOVDD
NIOVDD
NIOVDD
Table 4-5: Miscellaneous Pin Descriptions
Voltage
Voltage
Voltage
Table 4-4: Clock Input Pin Descriptions
IO
IO
IO
RESET#
RESET#
RESET#
State
State
State
0
Revision 10.3
Typically used as input clock source for bus clock and memory
clock
Typically used as input clock source for pixel clock
These inputs are used to configure the S1D13706 - see Table 4-7:
“Summary of Power-On/Reset Options,” on page 25.
Note: These pins are used for configuration of the S1D13706
and must be connected directly to IO V
General Purpose Output (possibly used for controlling the LCD
power). It may also be used for the MOD control signal of the Sharp
HR-TFT panel.
Test Enable input used for production test only (has type 1 pull-
down resistor with a typical value of 50Ω at 3.3V).
IO V
Section 4.3.1, “Host Interface” on page 18.
IO V
described in Section 4.3.2, “LCD Interface” on page 22, Section
4.3.3, “Clock Input” on page 24, and Section 4.3.4, “Miscellaneous”
on page 24.
2 Core V
7 V
SS
DD
DD
pins.
pins associated with the host interface pins as described in
pins associated with the non-host interface pins as
DD.
pins.
Description
Description
Description
Epson Research and Development
Hardware Functional Specification
DD
Vancouver Design Center
or V
Issue Date: 2008/12/16
SS
.

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