S1D13706F00A200 Epson, S1D13706F00A200 Datasheet - Page 136

• Manufacturer Part Number: S1D13706F00A200
• Description: LCD Drivers (QVGA) 320x240 LCD Controller @ 8bpp
• Manufacturer: Epson

Specifications of S1D13706F00A200

• Maximum Clock Frequency: 33 MHz
• Operating Supply Voltage: 1.8 V to 2.2 V, 3 V to 3.6 V
• Maximum Operating Temperature: + 85 C
• Package / Case: TQFP-100
• Attached Touch Screen: No
• Minimum Operating Temperature: - 40 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Page 136
12.2.1 Register Programming
S1D13706
X31B-A-001-10
Enable
Set SwivelView™ Mode Select bits (REG[71h] bits 1:0) to 01.
Display Start Address
The display refresh circuitry starts at pixel “B”, therefore the Main Window Display Start
Address registers (REG[74h], REG[75h], REG[76h]) must be programmed with the
address of pixel “B”. To calculate the value of the address of pixel “B” use the following
formula (assumes 8 bpp color depth).
Main Window Display Start Address bits 16:0
Line Address Offset
The Main Window Line Address Offset registers (REG[78h], REG[79h]) is based on the
display width and programmed using the following formula.
Main Window Line Address Offset bits 9:0
90° SwivelView™ Mode
= ((image address + (panel height x bpp ÷ 8)) ÷ 4) - 1
= ((0 + (320 pixels x 8 bpp ÷ 8)) ÷ 4) -1
= 79 (4Fh)
= display width in pixels ÷ (32 ÷ bpp)
= 320 pixels ÷ 32 ÷ 8 bpp
= 80 (50h)
Revision 10.3
Epson Research and Development
Hardware Functional Specification
Vancouver Design Center
Issue Date: 2008/12/16