S1D13706F00A200 Epson, S1D13706F00A200 Datasheet

LCD Drivers (QVGA) 320x240 LCD Controller @ 8bpp

S1D13706F00A200

Manufacturer Part Number
S1D13706F00A200
Description
LCD Drivers (QVGA) 320x240 LCD Controller @ 8bpp
Manufacturer
Epson
Datasheet

Specifications of S1D13706F00A200

Maximum Clock Frequency
33 MHz
Operating Supply Voltage
1.8 V to 2.2 V, 3 V to 3.6 V
Maximum Operating Temperature
+ 85 C
Package / Case
TQFP-100
Attached Touch Screen
No
Minimum Operating Temperature
- 40 C
Lead Free Status / RoHS Status
Lead free / RoHS Compliant

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
S1D13706F00A200
Manufacturer:
Epson Electronics America Inc-Semiconductor Div
Quantity:
10 000
S1D13706 Embedded Memory LCD Controller
Hardware Functional Specification
Document Number: X31B-A-001-10
Status: Revision 10.3
Issue Date: 2008/12/16
© SEIKO EPSON CORPORATION 1999-2008. All Rights Reserved.
Information in this document is subject to change without notice. You may download and use this document, but only for your own use in
evaluating Seiko Epson/EPSON products. You may not modify the document. Epson Research and Development, Inc. disclaims any
representation that the contents of this document are accurate or current. The Programs/Technologies described in this document may contain
material protected under U.S. and/or International Patent laws.
EPSON is a registered trademark of Seiko Epson Corporation. All other Trademarks are the property of their respective owners

Related parts for S1D13706F00A200

S1D13706F00A200 Summary of contents

Page 1

... Seiko Epson/EPSON products. You may not modify the document. Epson Research and Development, Inc. disclaims any representation that the contents of this document are accurate or current. The Programs/Technologies described in this document may contain material protected under U.S. and/or International Patent laws. EPSON is a registered trademark of Seiko Epson Corporation. All other Trademarks are the property of their respective owners ...

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... Page 2 S1D13706 X31B-A-001-10 Epson Research and Development Revision 10.3 Vancouver Design Center Hardware Functional Specification Issue Date: 2008/12/16 ...

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... Epson Research and Development Vancouver Design Center 1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 1.1 Scope . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 1.2 Overview Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 2 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 2.1 Integrated Frame Buffer 2.2 CPU Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 2.3 Display Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 2.4 Display Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 2.5 Display Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 2.6 Clock Source . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 2.7 Miscellaneous . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 3 Typical System Implementation Diagrams . . . . . . . . . . . . . . . . . . . . . . 10 4 Pins ...

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... TFT Panel Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68 6.4.10 160x160 Sharp ‘Direct’ HR-TFT Panel Timing (e.g. LQ031B1DDxx 6.4.11 320x240 Sharp ‘Direct’ HR-TFT Panel Timing (e.g. LQ039Q2DS01 6.4.12 160x240 Epson D-TFD Panel Timing (e.g. LF26SCR 6.4.13 320x240 Epson D-TFD Panel Timing (e.g. LF37SQR Clocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .84 7 ...

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... Epson Research and Development Vancouver Design Center 8.3.8 General IO Pins Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119 8.3.9 Pulse Width Modulation (PWM) Clock and Contrast Voltage (CV) Pulse Configuration Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123 9 Frame Rate Calculation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127 10 Display Data Formats 11 Look-Up Table Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129 11.1 Monochrome Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129 11.2 Color Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131 12 SwivelView™ ...

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... Page 6 S1D13706 X31B-A-001-10 Epson Research and Development Revision 10.3 Vancouver Design Center Hardware Functional Specification Issue Date: 2008/12/16 ...

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... The S1D13706 is a color/monochrome LCD graphics controller with an embedded 80K byte SRAM display buffer. While supporting all other panel types, the S1D13706 is the only LCD controller to directly interface to both the Epson D-TFD and the Sharp HR-TFT family of products thus removing the requirement of an external Timing Control IC. This ...

Page 8

... LCD interface. • 4/8/16-bit color LCD interface. • Active Matrix TFT interface. • 9/12/18-bit interface. • ‘Direct’ support for 18-bit Epson D-TFD interface. • ‘Direct’ support for 18-bit Sharp HR-TFT interface. S1D13706 X31B-A-001-10 Epson Research and Development Revision 10 ...

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... Epson Research and Development Vancouver Design Center 2.4 Display Modes • 1/2/4/8/16 bit-per-pixel (bpp) color depths. • gray shades using Frame Rate Modulation (FRM) and dithering on mono- chrome passive LCD panels. • 64K colors on passive STN panels. • 64K colors on active matrix LCD panels. ...

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... X31B-A-001-10 . Oscillator BS# M/R# CS# AB[16:1] DB[15:0] S1D13706 WE0# WE1# RD# RD/WR# WAIT# CLKI RESET# AB0 Revision 10.3 Epson Research and Development Vancouver Design Center 16-bit FPDAT[15:0] Single D[15:0] LCD FPFRAME FPFRAME Display FPLINE FPLINE FPSHIFT FPSHIFT DRDY MOD GPO Hardware Functional Specification Issue Date: 2008/12/16 ...

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... Epson Research and Development Vancouver Design Center Generic #2 BUS VDD A[27:17] Decoder CSn# A[16:0] D[15:0] WE# BHE# RD# WAIT# BUSCLK RESET# Figure 3-2: Typical System Diagram (Generic #2 Bus) SH-4 BUS A[25:17] Decoder CSn# A[16:1] D[15:0] WE0# WE1# BS# RD/WR# RD# RDY# CKIO RESET# VSS Figure 3-3: Typical System Diagram (Hitachi SH-4 Bus) ...

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... RESET# AB0 . Oscillator RD# WE0# M/R# CS# AB[16:1] DB[15:0] S1D13706 AB0 WE1# BS# RD/WR# WAIT# CLKI RESET# Revision 10.3 Epson Research and Development Vancouver Design Center 18-bit TFT FPDAT[17:0] D[17:0] Display FPFRAME FPFRAME FPLINE FPLINE FPSHIFT FPSHIFT DRDY DRDY GPO FPDAT[17:0] D[17:0] 18-bit SPS ...

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... Epson Research and Development Vancouver Design Center MC68K #2 BUS A[31:17] Decoder FC0, FC1 Decoder A[16:0] D[31:16] DS# AS# R/W# SIZ1 SIZ0 DSACK1# CLK RESET# Figure 3-6: Typical System Diagram (MC68K #2, Motorola 32-Bit 68030) REDCAP2 BUS HIOVDD A[21:17] Decoder CSn A[16:1] D[15:0] R/W ...

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... X31B-A-001-10 . Oscillator BS# RD/WR# M/R# CS# AB[16:1] DB[15:0] S1D13706 WE0# WE1# RD# WAIT# CLKI RESET# AB0 Revision 10.3 Epson Research and Development Vancouver Design Center 8-bit Single FPDAT[7:0] D[7:0] LCD FPSHIFT FPSHIFT Display FPFRAME FPFRAME FPLINE FPLINE DRDY MOD GPO Hardware Functional Specification Issue Date: 2008/12/16 ...

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... Epson Research and Development Vancouver Design Center 4 Pins 4.1 Pinout Diagram - TQFP15 - 100pin 76 NIOVDD 77 CLKI2 78 CNF7 79 CNF6 80 CNF5 81 CNF4 82 CNF3 83 CNF2 84 CNF1 85 CNF0 86 TESTEN 87 AB16 88 AB15 89 AB14 90 AB13 91 AB12 92 AB11 93 AB10 94 AB9 95 AB8 96 AB7 97 AB6 98 AB5 99 AB4 100 VSS Figure 4-1: Pinout Diagram - TQFP15 - 100pin (S1D13706F00A) ...

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... Figure 4-2: Pinout Diagram - Die Form (S1D13706D00A) Chip Size: 5.88 x 6.55 mm PAD size S1D13706 X31B-A-001-10 160 155 150 145 140 Y (0, μ m Revision 10.3 Epson Research and Development Vancouver Design Center 135 130 125 120 Unusable Pad 115 110 105 100 ...

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... Epson Research and Development Vancouver Design Center Table 4-1: Pinout Assignments - Die Form (S1D13706D00A) Pin No. Pad No. Pin Name 1 1 LVDD 2 3 AB3 3 5 AB2 4 8 AB1 5 10 AB0 WE0 WE1 RD/WR RESET VSS 15 34 CLKI 16 36 HVDD 17 39 ...

Page 18

... For DragonBall, this pin is not used and should be connected to VSS. See Table 4-8: “Host Bus Interface Pin Mapping,” on page 26 for summary. HIOVDD — System address bus bits 16-1. Revision 10.3 Epson Research and Development Vancouver Design Center Description Hardware Functional Specification Issue Date: 2008/12/16 ...

Page 19

... Epson Research and Development Vancouver Design Center Pin Name Type Pin # Cell 18-24, DB[15:0] IO LB2A 27-35 WE0 LIS WE1 LIS CS M/ LIS Hardware Functional Specification Issue Date: 2008/12/16 Table 4-2: Host Interface Pin Descriptions IO RESET# Voltage State Input data from the system data bus. ...

Page 20

... For MC68K #2, this pin inputs the bus size bit 1 (SIZ1). • For REDCAP2, this pin inputs the output enable (OE). • For DragonBall, this pin inputs the output enable (OE). See Table 4-8: “Host Bus Interface Pin Mapping,” on page 26 for summary. Revision 10.3 Epson Research and Development Vancouver Design Center Description . DD . ...

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... Epson Research and Development Vancouver Design Center Pin Name Type Pin # Cell WAIT LB2A RESET LIS Hardware Functional Specification Issue Date: 2008/12/16 Table 4-2: Host Interface Pin Descriptions IO RESET# Voltage State During a data transfer, this output pin is driven active to force the system to insert wait states ...

Page 22

... LCD backplane bias signal (MOD) for all other LCD panels See Table 4-9: “LCD Interface Pin Mapping,” on page 27 for summary. This pin has multiple functions. • PS for Sharp HR-TFT • XINH for Epson D-TFD NIOVDD 0 • General purpose IO pin 0 (GPIO0) • Hardware Video Invert See Table 4-9: “ ...

Page 23

... General purpose IO pin 4 (GPIO4) See Table 4-9: “LCD Interface Pin Mapping,” on page 27 for summary. This pin has multiple functions. • DD_P1 for Epson D-TFD NIOVDD 0 • General purpose IO pin 5 (GPIO5) See Table 4-9: “LCD Interface Pin Mapping,” on page 27 for summary ...

Page 24

... Section 4.3.2, “LCD Interface” on page 22, Section — — 4.3.3, “Clock Input” on page 24, and Section 4.3.4, “Miscellaneous” on page 24. — — 2 Core V pins. DD. — — pins. SS Revision 10.3 Epson Research and Development Vancouver Design Center Description Description Description Hardware Functional Specification Issue Date: 2008/12/16 ...

Page 25

... Epson Research and Development Vancouver Design Center 4.4 Summary of Configuration Options These pins are used for configuration of the S1D13706 and must be connected directly to NIOV state at any other time has no effect. Table 4-7: Summary of Power-On/Reset Options S1D13706 Configuration 1 (connected to NIOV Input Select host bus interface as follows: ...

Page 26

... CLK BS# AS# DD RD/WR# R/ Connected to RD Connected to WE0 WE1# UDS# WAIT#/ DTACK# RDY# RESET# RESET# Revision 10.3 Epson Research and Development Vancouver Design Center Motorola Motorola Motorola MC68EZ328/ MC68K #2 REDCAP2 MC68VZ328 DragonBall A[16:1] A[16:1] A[16: D[15:0] D[15:0] D[15:0] CSn CSX CLK CLK ...

Page 27

... Epson Research and Development Vancouver Design Center 4.6 LCD Interface Pin Mapping Monochrome Passive Panel Pin Name Single 4-bit 4-bit 8-bit FPFRAME FPLINE FPSHIFT DRDY MOD FPDAT0 driven 0 D0 driven 0 FPDAT1 driven 0 D1 driven 0 FPDAT2 driven 0 D2 driven 0 FPDAT3 driven 0 D3 ...

Page 28

... I = 6mA (Type 2) OL 12mA (Type 3) LVTTL Level max 2.0 DD LVTTL Level min DD LVTTL Schmitt LVTTL Schmitt LVTTL Schmitt Revision 10.3 Epson Research and Development Vancouver Design Center Units ° C ° C Min Typ Max 2.0 2.2 3.3 3.6 2.0 2.2 3.3 3.6 3 ...

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... Epson Research and Development Vancouver Design Center 6 A.C. Characteristics Conditions: 6.1 Clock Timing 6.1.1 Input Clocks Clock Input Waveform 90 10 Table 6-1: Clock Input Requirements for CLKI when CLKI to BCLK divide > 1 Symbol Parameter f Input Clock Frequency (CLKI) OSC T Input Clock period (CLKI) ...

Page 30

... Maximum internal requirements for clocks derived from CLKI2 must be considered when determining the frequency of CLKI2. See Section 6.1.2, “Internal Clocks” on page 31 for internal clock requirements. S1D13706 X31B-A-001-10 Parameter Parameter Revision 10.3 Epson Research and Development Vancouver Design Center 2.0V 3.3V Min Max Min Max ...

Page 31

... Epson Research and Development Vancouver Design Center 6.1.2 Internal Clocks Symbol Parameter f Bus Clock frequency BCLK f Memory Clock frequency MCLK f Pixel Clock frequency PCLK f PWM Clock frequency PWMCLK Note For further information on internal clocks, refer to Section 7, “Clocks” on page 84. Hardware Functional Specification ...

Page 32

... D[15:0](write) D[15:0](read) S1D13706 X31B-A-001-10 = Core Core V = 3.3V t11 t13 Figure 6-2: Generic #1 Interface Timing Revision 10.3 Epson Research and Development Vancouver Design Center = 2.0V. The 3.3V timings are based t10 t12 t15 t14 VALID Hardware Functional Specification Issue Date: 2008/12/16 ...

Page 33

... Epson Research and Development Vancouver Design Center Symbol Parameter f Bus Clock frequency CLK T Bus Clock period CLK t1 Clock pulse width high t2 Clock pulse width low A[16:1], M/R# setup to first CLK rising edge where CS and t3 either RD0#, RD1 WE0#, WE1 A[16:1], M/R# hold from either RD0#, RD1# or WE0#, WE1# ...

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... BUSCLK t3 SA[16:0] M/R#, SBHE# CS# MEMR# MEMW# IOCHRDY SD[15:0] (write) SD[15:0] (read) S1D13706 X31B-A-001- t11 t13 Figure 6-3: Generic #2 Interface Timing Revision 10.3 Epson Research and Development Vancouver Design Center t4 t6 t10 t12 t15 t14 VALID Hardware Functional Specification Issue Date: 2008/12/16 ...

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... Epson Research and Development Vancouver Design Center Symbol Parameter f Bus Clock frequency BUSCLK T Bus Clock period BUSCLK t1 Clock pulse width high t2 Clock pulse width low SA[16:0], M/R#, SBHE# setup to first BUSCLK rising edge t3 where CS and either MEMR MEMW SA[16:0], M/R#, SBHE# hold from either MEMR# or MEMW# ...

Page 36

... Hi-Z (write) D[15:0] Hi-Z (read) S1D13706 X31B-A-001- t10 t11 t15 Figure 6-4: Hitachi SH-4 Interface Timing Revision 10.3 Epson Research and Development Vancouver Design Center t4 t8 t14 t12 t13 Hi-Z t16 Hi-Z t17 t18 Hi-Z VALID Hardware Functional Specification Issue Date: 2008/12/16 ...

Page 37

... Epson Research and Development Vancouver Design Center Symbol Parameter f Clock frequency CKIO T Clock period CKIO t1 Clock pulse width low t2 Clock pulse width high t3 A[16:1], M/R#, RD/WR# setup to CKIO t4 A[16:1], M/R#, RD/WR# hold from CSn# t5 BS# setup t6 BS# hold t7 CSn# setup t8 CSn# high setup to CKIO ...

Page 38

... D[15:0] Hi-Z (write) D[15:0] Hi-Z (read) S1D13706 X31B-A-001- t10 t14 Figure 6-5: Hitachi SH-3 Interface Timing Revision 10.3 Epson Research and Development Vancouver Design Center t4 t8 t11 t13 Hi-Z t15 Hi-Z t16 t17 Hi-Z VALID Hardware Functional Specification Issue Date: 2008/12/16 ...

Page 39

... Epson Research and Development Vancouver Design Center Symbol Parameter f Bus Clock frequency CKIO T Bus Clock period CKIO t1 Bus Clock pulse width low t2 Bus Clock pulse width high t3 A[16:1], M/R#, RD/WR# setup to CKIO t4 CSn# high setup to CKIO t5 BS# setup t6 BS# hold t7 CSn# setup ...

Page 40

... DTACK# D[15:0](write) D[15:0](read) Figure 6-6: Motorola MC68K #1 Interface Timing S1D13706 X31B-A-001- t10 t13 t17 t19 Revision 10.3 Epson Research and Development Vancouver Design Center t11 t12 t14 t16 t18 t20 t21 VALID Hardware Functional Specification Issue Date: 2008/12/16 ...

Page 41

... Epson Research and Development Vancouver Design Center Table 6-9: Motorola MC68K #1 Interface Timing Symbol Parameter f Bus Clock Frequency CLK T Bus Clock period CLK t1 Clock pulse width high t2 Clock pulse width low A[16:1], M/R# setup to first CLK rising edge where CS AS UDS and LDS ...

Page 42

... For information on the implementation of the Motorola 68K #2 Host Bus Interface, see Interfacing To The Motorola MC68030 Microprocessor, document number X31B-G-013-xx. S1D13706 X31B-A-001- t10 t17 t19 Revision 10.3 Epson Research and Development Vancouver Design Center t11 t12 t14 t16 t18 t21 t20 VALID Hardware Functional Specification Issue Date: 2008/12/16 ...

Page 43

... Epson Research and Development Vancouver Design Center Table 6-10: Motorola MC68K #2 Interface Timing Symbol Parameter f Bus Clock frequency CLK T Bus Clock period CLK t1 Clock pulse width high t2 Clock pulse width low A[16:0], SIZ[1:0], M/R# setup to first CLK rising edge where ...

Page 44

... For further information on implementing the REDCAP2 microprocessor, see Interfac- ing to the Motorola REDCAP2 DSP with Integrated MCU, document number X31B-G-013-xx. S1D13706 X31B-A-001- VALID t10 t13 t12 Revision 10.3 Epson Research and Development Vancouver Design Center t4 t7 Hi-Z t11 t14 Hi-Z VALID Hardware Functional Specification Issue Date: 2008/12/16 ...

Page 45

... Epson Research and Development Vancouver Design Center Table 6-11: Motorola REDCAP2 Interface Timing Symbol Parameter f Bus Clock frequency CKO T Bus Clock period CKO t1 Bus Clock pulse width low t2 Bus Clock pulse width high t3 A[16:1], M/R#, R/W, CSn setup to CKO rising edge ...

Page 46

... Hi-Z D[15:0] (read) t16 DTACK Figure 6-9: Motorola DragonBall Interface with DTACK Timing S1D13706 X31B-A-001- t10 t12 t14 Revision 10.3 Epson Research and Development Vancouver Design Center t11 t13 Hi-Z t15 Hi-Z VALID t19 t17 t18 Hardware Functional Specification Issue Date: 2008/12/16 ...

Page 47

... Epson Research and Development Vancouver Design Center Table 6-12: Motorola DragonBall Interface with DTACK Timing Symbol Parameter f Bus Clock frequency CLKO T Bus Clock period CLKO t1 Clock pulse width high t2 Clock pulse width low A[16:1] setup 1st CLKO when CSX = 0 and either ...

Page 48

... D[15:0] Hi-Z (write) Hi-Z D[15:0] (read) Figure 6-10: Motorola DragonBall Interface without DTACK# Timing S1D13706 X31B-A-001- t10 t12 t15 t14 Revision 10.3 Epson Research and Development Vancouver Design Center t11 t13 Hi-Z t16 Hi-Z VALID Hardware Functional Specification Issue Date: 2008/12/16 ...

Page 49

... Epson Research and Development Vancouver Design Center Table 6-13: Motorola DragonBall Interface without DTACK Timing Symbol Parameter f Bus Clock frequency CLKO T Bus Clock period CLKO t1 Clock pulse width high t2 Clock pulse width low A[16:1] setup 1st CLKO when CSX = 0 and t3 either UWE/LWE ...

Page 50

... Note For HR-TFT Power-On/Off sequence information, see Connecting to the Sharp HR-TFT Panels, document number X31B-G-011-xx. For D-TFD Power-On/Off sequence information, see Connecting to the Epson D-TFD Panels, document number X31B-G-012-xx. S1D13706 X31B-A-001-10 t1 ...

Page 51

... Epson Research and Development Vancouver Design Center 6.3.2 Passive/TFT Power-Off Sequence GPO* Power Save Mode Enable** (REG[A0h] bit 0) LCD Signals*** *It is recommended to use the general purpose output pin GPO to control the LCD bias power. **The LCD power-off sequence is activated by programming the Power Save Mode Enable bit (REG[A0h] bit ...

Page 52

... REG[18h] bits 7- (REG[1Dh] bits 1-0, REG[1Ch] bits 7- REG[1Fh] bits 1-0, REG[1Eh] bits 7-0 REG[27h] bits 1-0, REG[26h] bits 7-0 (REG[24h] bits 6- Revision 10.3 Epson Research and Development Vancouver Design Center HPW Derived From Hardware Functional Specification Issue Date: 2008/12/16 ...

Page 53

... Epson Research and Development Vancouver Design Center 6.4.1 Generic STN Panel Timing VPW FPFRAME FPLINE 1 MOD (DRDY) FPDAT[17:0] FPLINE FPSHIFT 1PCLK 2 MOD (DRDY) HDPS FPDAT[17:0] Hardware Functional Specification Issue Date: 2008/12/ Frame) VDP Line) HPS HDP Figure 6-14: Generic STN Panel Timing Revision 10 ...

Page 54

... Polarity Bit (REG[20h] bit (active high) 1 *MOD is the MOD signal when (REG[11h] bits 5- (MOD toggles every FPFRAME) 2 *MOD is the MOD signal when (REG[11h] bits 5- (MOD toggles every n FPLINE) S1D13706 X31B-A-001-10 Epson Research and Development Revision 10.3 Vancouver Design Center Hardware Functional Specification Issue Date: 2008/12/16 ...

Page 55

... Epson Research and Development Vancouver Design Center 6.4.2 Single Monochrome 4-Bit Panel Timing FPFRAME FPLINE DRDY (MOD) FPDAT[7:4] Invalid FPLINE DRDY (MOD) FPSHIFT FPDAT7 Invalid FPDAT6 Invalid FPDAT5 Invalid FPDAT4 Invalid * Diagram drawn with 2 FPLINE vertical blank period Example timing for a 320x240 panel ...

Page 56

... HPS - (HDP + HDPS negative add t3 min 8. t14 = HDPS - (HPS + t4 min min S1D13706 X31B-A-001- Parameter ) min ), if negative add t3 min Revision 10.3 Epson Research and Development Vancouver Design Center t14 t11 t10 t12 t13 1 2 Min Typ Max note 2 Ts (note 1) note 3 note 4 ...

Page 57

... Epson Research and Development Vancouver Design Center 6.4.3 Single Monochrome 8-Bit Panel Timing FPFRAME FPLINE DRDY (MOD) FPDAT[7:0] Invalid FPLINE DRDY (MOD) FPSHIFT FPDAT7 Invalid FPDAT6 Invalid FPDAT5 Invalid FPDAT4 Invalid FPDAT3 Invalid FPDAT2 Invalid FPDAT1 Invalid FPDAT0 Invalid * Diagram drawn with 2 FPLINE vertical blank period ...

Page 58

... HPS - (HDP + HDPS negative add t3 min 8. t14 = HDPS - (HPS + t4 min min S1D13706 X31B-A-001- Parameter ) min ), if negative add t3 min Revision 10.3 Epson Research and Development Vancouver Design Center t14 t11 t10 t12 t13 1 2 Min Typ Max note 2 Ts (note 1) note 3 note 4 ...

Page 59

... Epson Research and Development Vancouver Design Center 6.4.4 Single Color 4-Bit Panel Timing FPFRAME FPLINE DRDY (MOD) FPDAT[7:4] Invalid FPLINE DRDY (MOD) .5Ts FPSHIFT Invalid 1-R1 FPDAT7 Invalid FPDAT6 Invalid 1-B1 FPDAT5 Invalid 1-R2 FPDAT4 Notes: - FPSHIFT uses extended low states in order to process 8 pixels in 6 FPSHIFT clocks ...

Page 60

... HPS - (HDP + HDPS) + 1.5), if negative add t3 min 8. t14 = HDPS - (HPS + t4 min min S1D13706 X31B-A-001- Parameter ) min ) + 1, if negative add t3 min Revision 10.3 Epson Research and Development Vancouver Design Center t14 t11 t10 t12 t13 1 2 Min Typ Max note 2 Ts (note 1) note 3 ...

Page 61

... Epson Research and Development Vancouver Design Center 6.4.5 Single Color 8-Bit Panel Timing (Format 1) FPFRAME FPLINE FPDAT[7:0] Invalid FPLINE 2Ts FPSHIFT FPSHIFT2 FPDAT7 Invalid FPDAT6 Invalid FPDAT5 Invalid FPDAT4 Invalid FPDAT3 Invalid FPDAT2 Invalid FPDAT1 Invalid FPDAT0 Invalid Notes: - The duty cycle of FPSHIFT changes in order to process 16 pixels in 6 FPSHIFT/FPSHIFT2 rising edges ...

Page 62

... HDPS - (HPS + t4 min min S1D13706 X31B-A-001- t6a t6b t7a t7b Parameter ) min min ), if negative add t3 min Revision 10.3 Epson Research and Development Vancouver Design Center t14 t11 t10 t12 t13 t12 t13 2 1 Min Typ Max note 2 note 3 note 4 note 5 ...

Page 63

... Epson Research and Development Vancouver Design Center 6.4.6 Single Color 8-Bit Panel Timing (Format 2) FPFRAME FPLINE DRDY (MOD) FPDAT[7:0] Invalid FPLINE DRDY (MOD) 2Ts FPSHIFT Ts FPDAT7 Invalid 1-R1 FPDAT6 Invalid 1-G1 FPDAT5 Invalid 1-B1 FPDAT4 Invalid 1-R2 FPDAT3 Invalid 1-G2 FPDAT2 ...

Page 64

... HPS - (HDP + HDPS negative add t3 min 8. t14 = HDPS - (HPS + t4 min min S1D13706 X31B-A-001- t14 Parameter ) min ), if negative add t3 min Revision 10.3 Epson Research and Development Vancouver Design Center t11 t10 t12 t13 1 2 Min Typ Max Units note 2 Ts (note 1) note 3 note 4 ...

Page 65

... Epson Research and Development Vancouver Design Center 6.4.7 Single Color 16-Bit Panel Timing FPFRAME FPLINE DRDY (MOD) FPDAT[15:0] Invalid FPLINE DRDY (MOD) 3Ts FPSHIFT Invalid 1-R1 - FPDAT15 Invalid 1-B1 FPDAT14 Invalid FPDAT13 1-G2 Invalid FPDAT12 1-R3 FPDAT7 Invalid 1-B3 FPDAT6 Invalid ...

Page 66

... HPS - (HDP + HDPS negative add t3 min 8. t14 = HDPS - (HPS + t4 min min S1D13706 X31B-A-001- t14 Parameter ) min ), if negative add t3 min Revision 10.3 Epson Research and Development Vancouver Design Center t11 t10 t12 t13 1 2 Min Typ Max note 2 Ts (note 1) note 3 note 4 note 5 ...

Page 67

... Epson Research and Development Vancouver Design Center 6.4.8 Generic TFT Panel Timing VPS FPFRAME FPLINE DRDY FPDAT[17:0] HPS HPW FPLINE FPSHIFT DRDY HDPS FPDAT[17:0] invalid VT = Vertical Total VPS = FPFRAME Pulse Start Position VPW = FPFRAME Pulse Width VDPS = Vertical Display Period Start Position ...

Page 68

... LINE1 HDP HNDP 1 invalid 1-1 1-2 Figure 6-28: 18-Bit TFT Panel Timing if negative add VT if negative add HT if negative add HT Revision 10.3 Epson Research and Development Vancouver Design Center VDP VNDP 1 LINE480 HNDP 2 1-320 invalid Hardware Functional Specification Issue Date: 2008/12/16 ...

Page 69

... Epson Research and Development Vancouver Design Center FPFRAME t3 FPLINE FPLINE DRDY t9 t10 t11 FPSHIFT FPDAT[17:0] Note: DRDY is used to indicate the first pixel Hardware Functional Specification Issue Date: 2008/12/ t12 invalid Figure 6-29: TFT A.C. Timing Revision 10 t13 t14 t15 t16 1 2 319 ...

Page 70

... HDPS - HPS 3. t8min = HPS - (HDP + HDPS) S1D13706 X31B-A-001-10 Table 6-23: TFT A.C. Timing Parameter if negative add HT if negative add HT Revision 10.3 Epson Research and Development Vancouver Design Center Min Typ Max Units VT Lines VPW Lines HPS Ts (note 1) ...

Page 71

... Epson Research and Development Vancouver Design Center 6.4.10 160x160 Sharp ‘Direct’ HR-TFT Panel Timing (e.g. LQ031B1DDxx) FPFRAME (SPS) FPLINE (LP) FPLINE (LP) FPSHIFT (CLK) FPDAT[17:0] GPIO3 (SPL) GPIO1 (CLS) t12 GPIO0 (PS) t13 GPIO2 (REV) Figure 6-30: 160x160 Sharp ‘Direct’ HR-TFT Panel Horizontal Timing ...

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... S1D13706 X31B-A-001-10 Parameter Revision 10.3 Epson Research and Development Vancouver Design Center Min Typ Max Units 13 Ts (note 1) 180 220 0 ...

Page 73

... Epson Research and Development Vancouver Design Center FPDAT[17:0] t4 FPFRAME (SPS) t5 GPIO1 (CLS) GPIO0 (PS) FPLINE (LP) FPSHIFT (CLK) GPIO1 (CLS) GPIO0 (PS) Figure 6-31: 160x160 Sharp ‘Direct’ HR-TFT Panel Vertical Timing Hardware Functional Specification Issue Date: 2008/12/ LINE1 LINE2 t11 t12 t10 t13 t14 Revision 10 ...

Page 74

... GPIO1 second pulse width t13 GPIO0 falling edge to FPLINE rising edge t14 GPIO0 low pulse width pixel clock period S1D13706 X31B-A-001-10 Parameter Revision 10.3 Epson Research and Development Vancouver Design Center Min Typ Max Units 203 264 Lines 40 Lines 160 ...

Page 75

... Epson Research and Development Vancouver Design Center 6.4.11 320x240 Sharp ‘Direct’ HR-TFT Panel Timing (e.g. LQ039Q2DS01) FPFRAME (SPS) FPLINE (LP) FPLINE (LP) FPSHIFT (CLK) FPDAT[17:0] GPIO3 (SPL) GPIO1 (CLS) t12 GPIO0 (PS) t13 GPIO2 (REV) Figure 6-32: 320x240 Sharp ‘Direct’ HR-TFT Panel Horizontal Timing ...

Page 76

... Vertical total period t1 Vertical display start position t2 Vertical display period t3 Vertical sync pulse width t4 S1D13706 X31B-A-001-10 Parameter t1 t3 LINE240 LINE1 LINE2 Parameter Revision 10.3 Epson Research and Development Vancouver Design Center Min Typ Max Units 14 Ts (note 1) 400 440 0.5 Ts 0.5 ...

Page 77

... FPDAT[17:0] (R,G,B) t7 t10 GPIO4 (RES) t11 GPIO1 (YSCL) GPIO0 (XINH) GPIO6 (YSCLD) GPIO2 (FR) GPIO3 (FRS) GPIO5 (DD_P1) Figure 6-34: 160x240 Epson D-TFD Panel Horizontal Timing Hardware Functional Specification Issue Date: 2008/12/ 160 t8 t9 t10 t12 t13 t17 Revision 10.3 t9 t11 t12 ...

Page 78

... DRDY (GCP) GCP Data Register 1 1 (REG[2Ch]) bit7 Figure 6-35: 160x240 Epson D-TFD Panel GCP Horizontal Timing Table 6-29: 160x240 Epson D-TFD Panel GCP Horizontal Timing Symbol Half of the horizontal total period t1 GCP clock period pixel clock period S1D13706 X31B-A-001-10 ...

Page 79

... GPIO0 (XINH) FPDAT[17:0] (R,G,B) GPIO2 (FR) (odd frame) GPIO2 (FR) (even frame) Figure 6-36: 160x240 Epson D-TFD Panel Vertical Timing Table 6-30: 160x240 Epson D-TFD Panel Vertical Timing Symbol FPFRAME pulse width t1 Horizontal total period t2 t3 Vertical display start pixel clock period ...

Page 80

... Page 80 6.4.13 320x240 Epson D-TFD Panel Timing (e.g. LF37SQR) t1 FPLINE (LP) t2 FPSHIFT (XSCL) FPDAT[17:0] (R,G,B) t7 t10 GPIO4 (RES) GPIO1 (YSCL) GPIO0 (XINH) GPIO6 (YSCLD) GPIO2 (FR) GPIO3 (FRS) GPIO5 (DD_P1) Figure 6-37: 320x240 Epson D-TFD Panel Horizontal Timing S1D13706 X31B-A-001- 320 t8 t9 ...

Page 81

... Epson Research and Development Vancouver Design Center Table 6-31: 320x240 Epson D-TFD Panel Horizontal Timing Symbol FPLINE pulse width t1 FPLINE falling edge to FPSHIFT start position t2 FPSHIFT active period t3 FPSHIFT start to first data t4 Horizontal display period t5 t6 Last data to FPSHIFT inactive FPLINE falling edge to GPIO4 first pulse falling edge ...

Page 82

... GPIO4 (RES) t2 DRDY (GCP) GCP Data Register 1 1 (REG[2Ch]) bit7 Figure 6-38: 320x240 Epson D-TFD Panel GCP Horizontal Timing Table 6-32: 320x240 Epson D-TFD Panel GCP Horizontal Timing Symbol Half of the horizontal total period t1 GCP clock period pixel clock period S1D13706 ...

Page 83

... GPIO0 (XINH) FPDAT[17:0] (R,G,B) GPIO2 (FR) (odd frame) GPIO2 (FR) (even frame) Figure 6-39: 320x240 Epson D-TFD Panel Vertical Timing Table 6-33: 320x240 Epson D-TFD Panel Vertical Timing Symbol FPFRAME pulse width t1 Horizontal total period t2 t3 Vertical display start pixel clock period ...

Page 84

... CNF[7: Table 7-2: MCLK Clock Selection Source Clock Options MCLK Selection BCLK REG[04h] bit 5 ÷ BCLK 2 REG[04h] bit 5 ÷ BCLK 3 REG[04h] bit 5 ÷ BCLK 4 REG[04h] bit 5 Revision 10.3 Epson Research and Development Vancouver Design Center Hardware Functional Specification Issue Date: 2008/12/16 ...

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... Epson Research and Development Vancouver Design Center 7.1.3 PCLK PCLK is the internal clock used to control the LCD panel. PCLK should be chosen to match the optimum frame rate of the LCD panel. See Section 9, “Frame Rate Calculation” on page 127 for details on the relationship between PCLK and frame rate. ...

Page 86

... Table 7-4: Relationship between MCLK and PCLK Color Depth (bpp 16/8/4/2/1 Table 7-5: PWMCLK Clock Selection Source Clock Options CLKI CLKI2 Revision 10.3 Epson Research and Development Vancouver Design Center MCLK to PCLK Relationship ≥ MCLK PCLK ÷ ≥ MCLK PCLK ÷ ...

Page 87

... Epson Research and Development Vancouver Design Center 7.2 Clock Selection The following diagram provides a logical representation of the S1D13706 internal clocks. CLKI CLKI2 Note 1 CNF[7:6] must be set at RESET#. Hardware Functional Specification Issue Date: 2008/12/16 00 ÷2 01 ÷3 10 ÷ CNF[7: REG[05h] bits 1 REG[B1h] bit 0 Figure 7-1: Clock Selection Revision 10 ...

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... Memory Clock (BCLK) (MCLK) Required Not Required Required Required Required Required Required Not Required Required Required Revision 10.3 Epson Research and Development Vancouver Design Center Pixel Clock PWM Clock (PCLK) (PWMCLK) 1 Not Required Not Required 1 Not Required Not Required 1 Not Required ...

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... Epson Research and Development Vancouver Design Center 8 Registers This section discusses how and where to access the S1D13706 registers. It also provides detailed information about the layout and usage of each register. 8.1 Register Mapping The S1D13706 registers are memory-mapped. When the system decodes the input pins as CS and M/ the registers may be accessed ...

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... REG[A9h] General Purpose IO Pins Configuration Register 1 REG[ADh] General Purpose IO Pins Status/Control Register 1 122 123 REG[B1h] PWM Clock / CV Pulse Configuration Register 126 REG[B3h] PWMOUT Duty Cycle Register Revision 10.3 Epson Research and Development Vancouver Design Center Register Pg 111 112 113 114 ...

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... Epson Research and Development Vancouver Design Center 8.3 Register Descriptions Unless specified otherwise, all register bits are set to 0 during power-on. 8.3.1 Read-Only Configuration Registers Revision Code Register REG[00h] Product Code Bits 5 Note The S1D13706 returns a value of 28h. bits 7-2 Product Code These are read-only bits that indicates the product code ...

Page 92

... Reserved. This bit must remain at 0. S1D13706 X31B-A-001- Table 8-2: MCLK Divide Selection Revision 10.3 Epson Research and Development Vancouver Design Center Read/Write n/a Reserved 2 1 BCLK to MCLK Frequency Ratio 1:1 2:1 3:1 4:1 Hardware Functional Specification Issue Date: 2008/12/16 ...

Page 93

... Epson Research and Development Vancouver Design Center Pixel Clock Configuration Register REG[05h] n/a PCLK Divide Select Bits 2 bits 6-4 PCLK Divide Select Bits [1:0] These bits determine the divide used to generate the Pixel Clock (PCLK) from the Pixel Clock Source. PCLK Divide Select Bits ...

Page 94

... Look-Up Table. Note The LUT entry is updated only when the LUT Write Address Register (REG[0Bh]) is written to. S1D13706 X31B-A-001- Revision 10.3 Epson Research and Development Vancouver Design Center Write Only n Write Only n Hardware Functional Specification Issue Date: 2008/12/16 ...

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... Epson Research and Development Vancouver Design Center Look-Up Table Red Write Data Register REG[0Ah] LUT Red Write Data Bits 5 bits 7-2 LUT Red Write Data Bits [5:0] This register contains the data to be written to the red component of the Look-Up Table. The data is stored in this register until a write to the LUT Write Address register (REG[0Bh]) moves the data into the Look-Up Table ...

Page 96

... If a write to the LUT Write Address register (REG[0Bh]) is made, the LUT Read Ad- dress register is automatically updated with the same value. S1D13706 X31B-A-001- LUT Read Address Bits 7 Revision 10.3 Epson Research and Development Vancouver Design Center Read Only n Read Only n Write Only 2 1 ...

Page 97

... Epson Research and Development Vancouver Design Center 8.3.4 Panel Configuration Registers Panel Type Register REG[10h] Panel Data Color/Mono. Panel Data Width Bits 1-0 Format Select Panel Select 7 6 bit 7 Panel Data Format Select When this bit = 0, 8-bit single color passive LCD panel data format 1 is selected. For AC timing see Section 6.4.5, “ ...

Page 98

... S1D13706 X31B-A-001-10 Table 8-7: LCD Panel Type Selection Panel Type HR-TFT 11 D-TFD MOD Rate Bits 5 Horizontal Total Bits 6 Revision 10.3 Epson Research and Development Vancouver Design Center STN TFT Read/Write 2 1 Read/Write 2 1 Hardware Functional Specification Issue Date: 2008/12/ ...

Page 99

... Epson Research and Development Vancouver Design Center Horizontal Display Period Register REG[14h] n bits 6-0 Horizontal Display Period Bits [6:0] These bits specify the LCD panel Horizontal Display Period (HDP pixel resolution. The Horizontal Display Period should be less than the Horizontal Total to allow for a suf- ficient Horizontal Non-Display Period. Horizontal Display Period in number of pixels = ((REG[14h] bits 6: × ...

Page 100

... For panel AC timing and timing parameter definitions, see Section 6.4, “Display Inter- face” on page 52. S1D13706 X31B-A-001-10 Vertical Total Bits 7 n Vertical Display Period Bits 7 n Revision 10.3 Epson Research and Development Vancouver Design Center Read/Write Read/Write Vertical Total Bits 9 Read/Write Read/Write Vertical Display Period Bits 9 ...

Page 101

... Epson Research and Development Vancouver Design Center Vertical Display Period Start Position Register 0 REG[1Eh Vertical Display Period Start Position Register 1 REG[1Fh bits 9-0 Vertical Display Period Start Position Bits [9:0] These bits specify the Vertical Display Period Start Position for panels in 1 line resolution. ...

Page 102

... For panel AC timing and timing parameter definitions, see Section 6.4, “Display Inter- face” on page 52. S1D13706 X31B-A-001-10 FPLINE Pulse Start Position Bits Revision 10.3 Epson Research and Development Vancouver Design Center Read/Write Read/Write FPLINE Pulse Start Position Bits 9 Read/Write FPFRAME Pulse Width Bits 2 ...

Page 103

... Epson Research and Development Vancouver Design Center FPFRAME Pulse Start Position Register 0 REG[26h FPFRAME Pulse Start Position Register 1 REG[27h bits 9-0 FPFRAME Pulse Start Position Bits [9:0] These bits specify the start position of the vertical sync signal line resolution. For passive panels, these bits must be set to 00h. ...

Page 104

... D-TFD GCP Data Bits [7:0] For D-TFD panel only. This register stores the data to be written to the GCP data bits and is controlled by the D-TFD GCP Index register (REG[28h]). For further information on the use of this register, see Connecting to the Epson D-TFD Panels, document number X31B-G-012-xx. Note The Panel Type bits (REG[10h] bits 1:0) must be set to 11 (D-TFD) for the GCP Data bits to have any hardware effect ...

Page 105

... Epson Research and Development Vancouver Design Center 8.3.5 Display Mode Registers Display Mode Register REG[70h] Hardware Dithering Display Blank Video Invert Disable Enable 7 6 bit 7 Display Blank When this bit = 0, the LCD display pipeline is enabled. When this bit = 1, the LCD display pipeline is disabled and all LCD data outputs are forced to zero (i ...

Page 106

... Video data is inverted after the Look-Up Table S1D13706 X31B-A-001-10 Table 8-8: Inverse Video Mode Select Options Software Video GPIO0 Invert Revision 10.3 Epson Research and Development Vancouver Design Center Video Data Normal Inverse Normal Inverse Hardware Functional Specification Issue Date: 2008/12/16 ...

Page 107

... Epson Research and Development Vancouver Design Center bits 2-0 Bit-per-pixel Select Bits [2:0] These bits select the color depth (bit-per-pixel) for the displayed data for both the main window and the PIP Note and 8 bpp color depths use the 18-bit LUT, allowing a maximum number of 256K available colors on TFT panels ...

Page 108

... Display Start Address register (REG[7Ch], REG[7Dh], TM orientations: TM Mode Select Options SwivelView Orientation Revision 10.3 Epson Research and Development Vancouver Design Center Data To LUT Serialization TM orientation as the main window. 0° (Normal) 90° 180° 270° Hardware Functional Specification ...

Page 109

... Epson Research and Development Vancouver Design Center Main Window Display Start Address Register 0 REG[74h Main Window Display Start Address Register 1 REG[75h Main Window Display Start Address Register 2 REG[76h bits 16-0 Main Window Display Start Address Bits [16:0] This register specifies the starting address, in DWORDS, for the LCD image in the display buffer for the main window ...

Page 110

... S1D13706 X31B-A-001-10 Main window Line Address Offset Bits 7 n display width in pixels ÷ (32 ÷ bpp) Revision 10.3 Epson Research and Development Vancouver Design Center Read/Write Read/Write Main window Line Address Offset Bits 9 Hardware Functional Specification ...

Page 111

... Epson Research and Development Vancouver Design Center 8.3.6 Picture-in-Picture Plus (PIP + PIP Window Display Start Address Register 0 REG[7C PIP Window Display Start Address Register 1 REG[7Dh PIP Window Display Start Address Register 2 REG[7Eh bits 16-0 PIP Window Display Start Address Bits [16:0] These bits form the 17-bit address for the starting double-word of the PIP Note that this is a double-word (32-bit) address ...

Page 112

... These bits have no effect unless the PIP 4). S1D13706 X31B-A-001-10 + PIP Window Line Address Offset Bits 7 n Window Enable bit is set to 1 (REG[71h] bit Revision 10.3 Epson Research and Development Vancouver Design Center Read/Write Read/Write + PIP Window Line Address Offset Bits 9 window. Note that this is Hardware Functional Specification ...

Page 113

... Epson Research and Development Vancouver Design Center + PIP Window X Start Position Register 0 REG[84h PIP Window X Start Position Register 1 REG[85h bits 9-0 PIP Window X Start Position Bits [9:0] These bits determine the X start position of the PIP panel. Due to the S1D13706 SwivelView feature, the X start position may not be a horizontal position value (only true in 0° ...

Page 114

... Table 8-12: 32-bit Address Increments for Color Depth Color Depth 1 bpp 2 bpp 4 bpp 8 bpp 16 bpp + Window Enable bit is set to 1 Revision 10.3 Epson Research and Development Vancouver Design Center Read/Write 2 1 Read/Write + PIP Window Y Start Position Bits 9 window in relation to the origin of the ...

Page 115

... Epson Research and Development Vancouver Design Center + PIP Window X End Position Register 0 REG[8Ch PIP Window X End Position Register 1 REG[8Dh bits 9-0 PIP Window X End Position Bits [9:0] These bits determine the X end position of the PIP panel. Due to the S1D13706 SwivelView feature, the X end position may not be a horizontal position value (only true in 0° ...

Page 116

... Table 8-14: 32-bit Address Increments for Color Depth Color Depth 1 bpp 2 bpp 4 bpp 8 bpp 16 bpp + Revision 10.3 Epson Research and Development Vancouver Design Center Read/Write 2 1 Read/Write + PIP Window Y End Position Bits 9 window in relation to the origin of the Pixel Increment (y) 32 ...

Page 117

... Epson Research and Development Vancouver Design Center 8.3.7 Miscellaneous Registers Power Save Configuration Register REG[A0h] Vertical Non- Display Period Status (RO bit 7 Vertical Non-Display Period Status This is a read-only status bit. When this bit = 0, the LCD panel output Vertical Display Period. When this bit = 1, the LCD panel output Vertical Non-Display Period. ...

Page 118

... This register contains general purpose read/write bits. These bits have no effect on hardware. S1D13706 X31B-A-001- Scratch Pad Bits 7 Scratch Pad Bits 15 Revision 10.3 Epson Research and Development Vancouver Design Center Read/Write Reserved Read/Write Read/Write Read/Write Hardware Functional Specification Issue Date: 2008/12/16 ...

Page 119

... Epson Research and Development Vancouver Design Center 8.3.8 General IO Pins Registers General Purpose IO Pins Configuration Register 0 REG[A8h] GPIO6 Pin IO GPIO5 Pin IO n/a Configuration Configuration 7 6 Note 1 If CNF3 = 0 at RESET#, then all GPIO pins are configured as outputs only and this register has no effect. This case allows the GPIO pins to be used by the HR-TFT/D-TFD panel interfaces. For a summary of GPIO usage for HR-TFT/D-TFD, see Table 4-9: “ ...

Page 120

... When a D-TFD panel is enabled (REG[10h] bits 1:0 = 11), GPIO4 outputs the RES signal automatically and writing to this bit has no effect. S1D13706 X31B-A-001-10 GPIO4 Pin IO GPIO3 Pin IO Status Status Revision 10.3 Epson Research and Development Vancouver Design Center Read/Write GPIO2 Pin IO GPIO1 Pin IO GPIO0 Pin IO Status Status Status 2 1 Hardware Functional Specification ...

Page 121

... Epson Research and Development Vancouver Design Center bit 3 GPIO3 Pin IO Status When neither a D-TFD panel or a HR-TFT are selected (REG[10h] bits 1:0) and GPIO3 is configured as an output, writing this bit drives GPIO3 high and writing this bit drives GPIO3 low. When neither a D-TFD panel or a HR-TFT are selected (REG[10h] bits 1:0) and GPIO3 is configured as an input, a read from this bit returns the status of GPIO3 ...

Page 122

... Writing this bit drives GPO to high. Note Many implementations use the GPO pin to control the LCD bias power (see Section 6.3, “LCD Power Sequencing” on page 50). S1D13706 X31B-A-001-10 n Revision 10.3 Epson Research and Development Vancouver Design Center Read/Write Hardware Functional Specification Issue Date: 2008/12/16 ...

Page 123

... Epson Research and Development Vancouver Design Center 8.3.9 Pulse Width Modulation (PWM) Clock and Contrast Voltage (CV) Pulse Configuration Registers PWM Clock Divider PWMCLK Clock Source / PWM Clock Divide Select value CV Pulse Divider Clock Source / Pulse Divide Select value Figure 8-2: PWM Clock/CV Pulse Block Diagram Note For further information on PWMCLK, see Section 7.1.4, “ ...

Page 124

... See description for bit 3. S1D13706 X31B-A-001-10 Table 8-16: CV Pulse Control Bit 0 CV Pulse circuitry enabled 1 (controlled by REG[B1h] and REG[B2h Revision 10.3 Epson Research and Development Vancouver Design Center Result CVOUT forced low CVOUT forced high Hardware Functional Specification Issue Date: 2008/12/16 ...

Page 125

... Epson Research and Development Vancouver Design Center PWM Clock / CV Pulse Configuration Register REG[B1h] PWM Clock Divide Select Bits 3 bits 7-4 PWM Clock Divide Select Bits [3:0] The value of these bits represents the power which the selected PWM clock source is divided. Table 8-17: PWM Clock Divide Select Options ...

Page 126

... PWMOUT Duty Cycle Bits 7 High for 1 out of 256 clock periods High for 2 out of 256 clock periods High for 255 out of 256 clock periods Revision 10.3 Epson Research and Development Vancouver Design Center Read/Write 2 1 Read/Write 2 1 PWMOUT Duty Cycle Always Low ...

Page 127

... Epson Research and Development Vancouver Design Center 9 Frame Rate Calculation The following formula is used to calculate the display frame rate. Where: f PCLK HT VT Hardware Functional Specification Issue Date: 2008/12/16 f PCLK FrameRate = ------------------------------- - ( HT ) × PClk frequency (Hz) = Horizontal Total = ((REG[12h] bits 6- Pixels = Vertical Total = ((REG[19h] bits 1-0, REG[18h] bits 7- Lines Revision 10 ...

Page 128

... Bypasses LUT Display Buffer , represent the red, green, and blue color components Revision 10.3 Epson Research and Development Vancouver Design Center LUT P = RGB value from LUT n Index ( Panel Display LUT P = RGB value from LUT n Index ( Panel Display LUT P = RGB value from LUT ...

Page 129

... Epson Research and Development Vancouver Design Center 11 Look-Up Table Architecture The following figures are intended to show the display data output path only. Note When Video Data Invert is enabled the video data is inverted after the Look-Up Table. 11.1 Monochrome Modes The green Look-Up Table (LUT) is used for all monochrome modes. ...

Page 130

... bit-per-pixel data from Display Buffer Figure 11-4: 8 Bit-per-pixel Monochrome Mode Data Output Path S1D13706 X31B-A-001-10 Epson Research and Development 0000 0001 0010 0011 0100 0101 0110 6-bit Gray Data 0111 1000 1001 1010 1011 1100 1101 1110 1111 = unused Look-Up Table entries ...

Page 131

... Epson Research and Development Vancouver Design Center 16 Bit-Per-Pixel Monochrome Mode The LUT is bypassed and the green data is directly mapped for this color depth– See “Display Data Formats” on page 128.. 11.2 Color Modes 1 Bit-Per-Pixel Color Red Look-Up Table 256x6 00 01 ...

Page 132

... Blue Look-Up Table 256x6 bit-per-pixel data from Image Buffer Figure 11-6: 2 Bit-Per-Pixel Color Mode Data Output Path S1D13706 X31B-A-001-10 Epson Research and Development 00 6-bit Red Data 6-bit Green Data 6-bit Blue Data unused Look-Up Table entries Revision 10.3 Vancouver Design Center ...

Page 133

... Epson Research and Development Vancouver Design Center 4 Bit-Per-Pixel Color Red Look-Up Table 256x6 Green Look-Up Table 256x6 Blue Look-Up Table 256x6 bit-per-pixel data from Image Buffer Figure 11-7: 4 Bit-Per-Pixel Color Mode Data Output Path Hardware Functional Specification Issue Date: 2008/12/16 0000 ...

Page 134

... Figure 11-8: 8 Bit-per-pixel Color Mode Data Output Path 16 Bit-Per-Pixel Color Mode The LUT is bypassed and the color data is directly mapped for this color depth– See “Display Data Formats” on page 128. S1D13706 X31B-A-001-10 Epson Research and Development 0000 0000 0000 0001 0000 0010 0000 0011 0000 0100 ...

Page 135

... Epson Research and Development Vancouver Design Center 12 SwivelView™ 12.1 Concept Most computer displays are refreshed in landscape orientation – from left to right and top to bottom. Computer images are stored in the same manner. SwivelView™ is designed to rotate the displayed image on an LCD by 90°, 180°, or 270° counter-clockwise direction. The rotation is done in hardware and is transparent to the user for all display buffer reads and writes. By processing the rotation in hardware, SwivelView™ ...

Page 136

... Revision 10.3 Epson Research and Development Vancouver Design Center Hardware Functional Specification Issue Date: 2008/12/16 ...

Page 137

... Epson Research and Development Vancouver Design Center 12.3 180° SwivelView™ The following figure shows how the programmer sees a 480x320 landscape image and how the image is being displayed. The application image is written to the S1D13706 in the following sense: A–B–C–D. The display is refreshed by the S1D13706 in the following sense: D-C-B-A ...

Page 138

... Figure 12-3: Relationship Between The Screen Image and the Image Refreshed in 270° SwivelView. S1D13706 X31B-A-001-10 = display width in pixels ÷ (32 ÷ bpp) = 480 pixels ÷ 32 ÷ 8 bpp = 120 (78h) B display start address (panel origin) Revision 10.3 Epson Research and Development Vancouver Design Center 480 image refreshed by S1D13706 Hardware Functional Specification Issue Date: 2008/12/16 ...

Page 139

... Epson Research and Development Vancouver Design Center 12.4.1 Register Programming 270° SwivelView™ Mode Enable Set SwivelView™ Mode Select bits (REG[71h] bits 1:0) to 11. The display refresh circuitry starts at pixel “C”, therefore the Main Window Display Start Address registers (REG[74h], REG[75h], REG[76h]) must be programmed with the address of pixel “ ...

Page 140

... PIP window y end position (REG[91h],REG[90h]) main-window + PIP window + PIP window x end position (REG[8Dh],REG[8Ch]) Revision 10.3 Epson Research and Development Vancouver Design Center + window) within the main window within a main window and the Hardware Functional Specification Issue Date: 2008/12/16 ...

Page 141

... Epson Research and Development Vancouver Design Center 13.2 With SwivelView Enabled 13.2.1 SwivelView 90° TM 90° SwivelView + PIP window x end position (REG[8Dh],REG[8Ch]) Figure 13-2: Picture-in-Picture Plus with SwivelView 90° enabled 13.2.2 SwivelView 180° TM 180° SwivelView PIP + PIP window y end position (REG[91h],REG[90h]) Figure 13-3: Picture-in-Picture Plus with SwivelView 180° ...

Page 142

... PIP window x start position (REG[85h],REG[84h]) panel’s origin Figure 13-4: Picture-in-Picture Plus with SwivelView 270° enabled S1D13706 X31B-A-001-10 Epson Research and Development main-window + PIP window + PIP window x end position (REG[8Dh],REG[8Ch]) Revision 10.3 Vancouver Design Center ...

Page 143

... Epson Research and Development Vancouver Design Center 14 Big-Endian Bus Interface 14.1 Byte Swapping Bus Data The display buffer and register architecture of the S1D13706 is inherently little-endian host bus interface is configured as big-endian (CNF4 = 1 at reset), bus accesses are automatically handled by byte swapping all read/write data to/from the internal display buffer and registers ...

Page 144

... S1D13706 X31B-A-001-10 D[15:8] D[7: CPU Data Byte Swap Byte Swap Display Buffer (Little-Endian) Figure 14-1: Byte-swapping for 16 Bpp Revision 10.3 Epson Research and Development Vancouver Design Center Display Buffer Address Display Data aabb ccdd Hardware Functional Specification Issue Date: 2008/12/16 ...

Page 145

... Epson Research and Development Vancouver Design Center 14.1.2 1/2/4/8 Bpp Color Depth For 1/2/4/8 bpp color depth, byte swapping must be performed on the bus data but not the display data. For 1/2/4/8 bpp color depth, the Display Data Byte Swap bit (REG[71h] bit 6) must be set to 0 ...

Page 146

... Table 15-1: Power Save Mode Function Summary IO Access Possible? Memory Writes Possible? Memory Reads Possible? Sequence Controller Running? Display Active? LCD I/F Outputs PWMCLK GPIO Pins configured for HR-TFT/D-TFD Revision 10.3 Epson Research and Development Vancouver Design Center Software Normal Power Save Yes Yes 1 Yes Yes ...

Page 147

... Epson Research and Development Vancouver Design Center 16 Mechanical Data 100-pin TQFP15 surface mount package 76 100 All dimensions in mm Figure 16-1: Mechanical Data 100pin TQFP15 (S1D13706F00A) Hardware Functional Specification Issue Date: 2008/12/16 ± 0.4 16.0 ± 0.1 14.0 75 Index 1 + 0.1 0.18 0.5 - 0.05 ± ...

Page 148

... The following documents contain additional information related to the S1D13706. Document numbers are listed in parenthesis after the document name. All documents can be found at the Epson Research and Development Website at www.erd.epson.com. • 13706CFG Configuration Utility Users Manual (X31B-B-001-xx) • 13706SHOW Demonstration Program Users Manual (X31B-B-002-xx) • ...

Page 149

... EPSON HONG KONG LTD. 20/F, Harbour Centre, 25 Harbour Road Wanchai, Hong Kong Phone: +852-2585-4600 FAX: +852-2827-4346 Telex: 65542 EPSCO HX EPSON TAIWAN TECHNOLOGY & TRADING LTD. 14F, No. 7, Song Ren Road, Taipei 110, TAIWAN Phone: +886-2-8786-6688 FAX: +886-2-8786-6660 EPSON SINGAPORE PTE., LTD. ...

Page 150

... Host Interface timing diagrams changed the t7 values from max. to min and added notes 2-5 • section 19, updated Japan sales group name and Taiwan office address S1D13706 X31B-A-001-10 Change Record Revision 10.3 Epson Research and Development Vancouver Design Center Hardware Functional Specification Issue Date: 2008/12/16 ...

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