S1D13706F00A200 Epson, S1D13706F00A200 Datasheet - Page 41

• Manufacturer Part Number: S1D13706F00A200
• Description: LCD Drivers (QVGA) 320x240 LCD Controller @ 8bpp
• Manufacturer: Epson

Specifications of S1D13706F00A200

• Maximum Clock Frequency: 33 MHz
• Operating Supply Voltage: 1.8 V to 2.2 V, 3 V to 3.6 V
• Maximum Operating Temperature: + 85 C
• Package / Case: TQFP-100
• Attached Touch Screen: No
• Minimum Operating Temperature: - 40 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Epson Research and Development
Vancouver Design Center
1. t17 is the delay from when data is placed on the bus until the data is latched into the write buffer.
2. When
3. When
4. When
5. When
Hardware Functional Specification
Issue Date: 2008/12/16
Symbol
T
f
t7a
t7b
t7c
t7d
t10
t11
t12
t13
t14
t15
t16
t17
t18
t19
t20
t21
CLK
CLK
t1
t2
t3
t4
t5
t6
t8
t9
Bus Clock Frequency
Bus Clock period
Clock pulse width high
Clock pulse width low
A[16:1], M/R# setup to first CLK rising edge where CS# = 0,
AS# = 0, UDS# = 0, and LDS# = 0
A[16:1], M/R# hold from AS# rising edge
CS# setup to CLK rising edge while CS#, AS#, UDS#/LDS# = 0
CS# hold from AS# rising edge
AS# asserted for MCLK = BCLK when DTACK# is not used (see
Note 2)
AS# asserted for MCLK = BCLK ÷ 2 when DTACK# is not used
(see Note 3)
AS# asserted for MCLK = BCLK ÷ 3 when DTACK# is not used
(see Note 4)
AS# asserted for MCLK = BCLK ÷ 4 when DTACK# is not used
(see Note 5)
AS# setup to CLK rising edge while CS#, AS#, UDS#/LDS# = 0
AS# setup to CLK rising edge
UDS#/LDS# setup to CLK rising edge while CS#, AS#,
UDS#/LDS# = 0
UDS#/LDS# high setup to CLK rising edge
First CLK rising edge where AS# = 1 to DTACK# high impedance
R/W# setup to CLK rising edge before all CS#, AS#, UDS# and/or
LDS# = 0
R/W# hold from AS# rising edge
AS# = 0 and CS# = 0 to DTACK# driven high
AS# rising edge to DTACK# rising edge
D[15:0] valid to third CLK rising edge where CS# = 0, AS# = 0 and
either UDS# = 0 or LDS# = 0 (write cycle) (see note 1)
D[15:0] hold from DTACK# falling edge (write cycle)
UDS# = 0 and/or LDS# = 0 to D[15:0] driven (read cycle)
DTACK# falling edge to D[15:0] valid (read cycle)
UDS#, LDS# rising edge to D[15:0] high impedance (read cycle)
DTACK#
DTACK#
DTACK#
DTACK#
is used, the Host will assert AS# for up to 8T
is used, the Host will assert AS# for up to 11T
is used, the Host will assert AS# for up to 13T
is used, the Host will assert AS# for up to 18T
Table 6-9: Motorola MC68K #1 Interface Timing
Parameter
Revision 10.3
CLK
CLK
CLK
CLK
.
.
.
.
1/f
22.5
22.5
Min
11
13
18
CLK
1
0
0
0
8
1
1
3
3
5
0
0
4
6
1
0
4
5
2.0V
Max
20
40
23
39
27
33
0
1/f
Min
11
13
18
9
9
1
0
1
0
8
1
2
1
2
3
1
0
3
4
0
0
3
3
CLK
3.3V
Max
50
14
13
16
13
13
2
X31B-A-001-10
S1D13706
T
T
T
T
Page 41
Unit
MHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
CLK
CLK
CLK
CLK