S1D13706F00A200 Epson, S1D13706F00A200 Datasheet - Page 49

• Manufacturer Part Number: S1D13706F00A200
• Description: LCD Drivers (QVGA) 320x240 LCD Controller @ 8bpp
• Manufacturer: Epson

Specifications of S1D13706F00A200

• Maximum Clock Frequency: 33 MHz
• Operating Supply Voltage: 1.8 V to 2.2 V, 3 V to 3.6 V
• Maximum Operating Temperature: + 85 C
• Package / Case: TQFP-100
• Attached Touch Screen: No
• Minimum Operating Temperature: - 40 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Epson Research and Development
Vancouver Design Center
1. The MC68EZ328 cannot support the MCLK = BCLK ÷ 3 and MCLK = BCLK ÷ 4 settings without DTACK.
2. t12 is the delay from when data is placed on the bus until the data is latched into the write buffer.
Hardware Functional Specification
Issue Date: 2008/12/16
Symbol
T
f
CLKO
t15a
t15b
t15c
t15d
CLKO
t5a
t5b
t5d
t10
t11
t12
t13
t14
t16
t5c
t1
t2
t3
t4
t6
t7
t8
t9
Bus Clock frequency
Bus Clock period
Clock pulse width high
Clock pulse width low
A[16:1] setup 1st CLKO when CSX = 0 and
either UWE/LWE or OE = 0
A[16:1] hold from CSX rising edge
CSX asserted for MCLK = BCLK
(CPU wait state register should be programmed
to 4 wait states)
CSX asserted for MCLK = BCLK ÷ 2
(CPU wait state register should be programmed
to 6 wait states)
CSX asserted for MCLK = BCLK ÷ 3
(CPU wait state register should be programmed
to 10 wait states)
CSX asserted for MCLK = BCLK ÷ 4
(CPU wait state register should be programmed
to 12 wait states)
CSX setup to CLKO rising edge
CSX rising edge setup to CLKO rising edge
UWE/LWE setup to CLKO rising edge
UWE/LWE rising edge to CSX rising edge
OE setup to CLKO rising edge
OE hold from CSX rising edge
D[15:0] setup to 3rd CLKO after CSX, UWE/LWE
asserted (write cycle) (see note 2)
CSX rising edge to D[15:0] output Hi-Z (write
cycle)
Falling edge of OE to D[15:0] driven (read cycle)
1st CLKO rising edge after OE and CSX
asserted low to D[15:0] valid for MCLK = BCLK
(read cycle)
1st CLKO rising edge after OE and CSX
asserted low to D[15:0] valid for MCLK = BCLK ÷
2 (read cycle)
1st CLKO rising edge after OE and CSX
asserted low to D[15:0] valid for MCLK = BCLK ÷
3 (read cycle)
1st CLKO rising edge after OE and CSX
asserted low to D[15:0] valid for MCLK = BCLK ÷
4 (read cycle)
CLKO rising edge to D[15:0] output Hi-Z
(read cycle)
Parameter
Table 6-13: Motorola DragonBall Interface without DTACK Timing
Revision 10.3
1/f
Note 1
Note 1
28.1
28.1
Min
11
CLKO
0
0
8
0
0
1
0
1
0
1
0
4
4
2.0V
5.5T
8T
9.5T
13T
Max
+ 17
CLKO
MC68EZ328
16
—
—
30
+ 4
+ 9
21
19
CLKO
CLKO
CLKO
+
1/f
Note 1
Note 1
28.1
28.1
Min
11
CLKO
0
0
8
0
0
0
0
1
0
0
0
3
2
3.3V
10.5T
14.5T
5.5T
8.5T
Max
+ 20
+ 20
+ 20
+ 20
16
15
12
CLKO
CLKO
CLKO
CLKO
1/f
22.5
22.5
Min
11
13
17
CLKO
0
0
8
0
0
1
0
1
0
1
0
4
4
2.0V
5.5T
8T
9.5T
13T
Max
MC68VZ328
CLKO
+ 17
20
30
+ 4
+ 9
21
19
CLKO
CLKO
CLKO
+
1/f
13.6
13.6
Min
11
13
17
CLKO
0
0
8
0
0
0
0
1
0
0
0
3
2
X31B-A-001-10
3.3V
S1D13706
10.5T
14.5T
5.5T
8.5T
Max
+ 20
+ 20
+ 20
+ 20
Page 49
33
15
12
CLKO
CLKO
CLKO
CLKO
T
T
T
T
MHz
Unit
CLKO
CLKO
CLKO
CLKO
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns