S1D13706F00A200 Epson, S1D13706F00A200 Datasheet - Page 86

• Manufacturer Part Number: S1D13706F00A200
• Description: LCD Drivers (QVGA) 320x240 LCD Controller @ 8bpp
• Manufacturer: Epson

Specifications of S1D13706F00A200

• Maximum Clock Frequency: 33 MHz
• Operating Supply Voltage: 1.8 V to 2.2 V, 3 V to 3.6 V
• Maximum Operating Temperature: + 85 C
• Package / Case: TQFP-100
• Attached Touch Screen: No
• Minimum Operating Temperature: - 40 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Page 86
7.1.4 PWMCLK
S1D13706
X31B-A-001-10
Note
There is a relationship between the frequency of MCLK and PCLK that must be
maintained.
PWMCLK is the internal clock used by the Pulse Width Modulator for output to the panel.
The source clock options for PWMCLK may be selected as in the following table.
For further information on controlling PWMCLK, see Section 8.3.9, “Pulse Width
Modulation (PWM) Clock and Contrast Voltage (CV) Pulse Configuration Registers” on
page 123.
The S1D13706 provides Pulse Width Modulation output on the pin PWMOUT.
PWMOUT can be used to control LCD panels which support PWM control of the back-
light inverter.
SwivelView 90° and 270°
SwivelView Orientation
SwivelView 0° and 180°
Table 7-4: Relationship between MCLK and PCLK
Source Clock Options
Table 7-5: PWMCLK Clock Selection
Revision 10.3
CLKI2
Color Depth (bpp)
CLKI
16/8/4/2/1
16
8
4
2
1
PWMCLK Selection
REG[B1h] bit 0 = 0
REG[B1h] bit 0 = 1
MCLK to PCLK Relationship
f
f
f
f
f
MCLK
MCLK
MCLK
MCLK
MCLK
f
MCLK
Epson Research and Development
≥ f
≥ f
≥ f
≥ f
≥ 1.25f
Hardware Functional Specification
≥ f
PCLK
PCLK
PCLK
PCLK
PCLK
PCLK
÷
÷
÷
÷
Vancouver Design Center
16
2
4
8
Issue Date: 2008/12/16