S1D13706F00A200 Epson, S1D13706F00A200 Datasheet - Page 92

• Manufacturer Part Number: S1D13706F00A200
• Description: LCD Drivers (QVGA) 320x240 LCD Controller @ 8bpp
• Manufacturer: Epson

Specifications of S1D13706F00A200

• Maximum Clock Frequency: 33 MHz
• Operating Supply Voltage: 1.8 V to 2.2 V, 3 V to 3.6 V
• Maximum Operating Temperature: + 85 C
• Package / Case: TQFP-100
• Attached Touch Screen: No
• Minimum Operating Temperature: - 40 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Page 92
8.3.2 Clock Configuration Registers
bits 5-4
bit 0
S1D13706
X31B-A-001-10
Memory Clock Configuration Register
REG[04h]
7
n/a
6
MCLK Divide Select Bits [1:0]
These bits determine the divide used to generate the Memory Clock (MCLK) from the
Bus Clock (BCLK).
Reserved.
This bit must remain at 0.
MCLK Divide Select Bits 1-0
MCLK Divide Select Bits
5
00
01
10
11
Table 8-2: MCLK Divide Selection
4
Revision 10.3
3
BCLK to MCLK Frequency Ratio
n/a
2
Epson Research and Development
1:1
2:1
3:1
4:1
Hardware Functional Specification
1
Vancouver Design Center
Issue Date: 2008/12/16
Read/Write
Reserved
0