S1D13706F00A200 Epson, S1D13706F00A200 Datasheet - Page 93

• Manufacturer Part Number: S1D13706F00A200
• Description: LCD Drivers (QVGA) 320x240 LCD Controller @ 8bpp
• Manufacturer: Epson

Specifications of S1D13706F00A200

• Maximum Clock Frequency: 33 MHz
• Operating Supply Voltage: 1.8 V to 2.2 V, 3 V to 3.6 V
• Maximum Operating Temperature: + 85 C
• Package / Case: TQFP-100
• Attached Touch Screen: No
• Minimum Operating Temperature: - 40 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Epson Research and Development
Vancouver Design Center
bits 6-4
bits 1-0
Hardware Functional Specification
Issue Date: 2008/12/16
Pixel Clock Configuration Register
REG[05h]
n/a
7
6
PCLK Divide Select Bits 2-0
PCLK Divide Select Bits [1:0]
These bits determine the divide used to generate the Pixel Clock (PCLK) from the Pixel
Clock Source.
PCLK Source Select Bits [1:0]
These bits determine the source of the Pixel Clock (PCLK).
PCLK Source Select Bits
PCLK Divide Select Bits
5
1XX
000
001
010
011
00
01
10
11
Table 8-4: PCLK Source Selection
Table 8-3: PCLK Divide Selection
4
Revision 10.3
3
PCLK Source to PCLK Frequency Ratio
n/a
2
PCLK Source
MCLK
CLKI2
BCLK
CLKI
1:1
2:1
3:1
4:1
8:1
PCLK Source Select Bits 1-0
1
Read/Write
X31B-A-001-10
S1D13706
0
Page 93