S1D13706F00A200 Epson, S1D13706F00A200 Datasheet - Page 45

LCD Drivers (QVGA) 320x240 LCD Controller @ 8bpp

S1D13706F00A200

Manufacturer Part Number
S1D13706F00A200
Description
LCD Drivers (QVGA) 320x240 LCD Controller @ 8bpp
Manufacturer
Epson
Datasheet

Specifications of S1D13706F00A200

Maximum Clock Frequency
33 MHz
Operating Supply Voltage
1.8 V to 2.2 V, 3 V to 3.6 V
Maximum Operating Temperature
+ 85 C
Package / Case
TQFP-100
Attached Touch Screen
No
Minimum Operating Temperature
- 40 C
Lead Free Status / RoHS Status
Lead free / RoHS Compliant

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
S1D13706F00A200
Manufacturer:
Epson Electronics America Inc-Semiconductor Div
Quantity:
10 000
Epson Research and Development
Vancouver Design Center
1. t8 is the delay from when data is placed on the bus until the data is latched into the write buffer.
Hardware Functional Specification
Issue Date: 2008/12/16
Symbol
T
f
t13a
t13b
t13c
t13d
CKO
t5a
t5b
t5c
t5d
t10
t11
t12
t14
CKO
t1
t2
t3
t4
t6
t7
t8
t9
Bus Clock frequency
Bus Clock period
Bus Clock pulse width low
Bus Clock pulse width high
A[16:1], M/R#, R/W, CSn setup to CKO rising edge
A[16:1], M/R#, R/W, CSn hold from CKO rising edge
CSn asserted for MCLK = BCLK
CSn asserted for MCLK = BCLK ÷ 2
CSn asserted for MCLK = BCLK ÷ 3
CSn asserted for MCLK = BCLK ÷ 4
EB0, EB1 asserted to CKO rising edge (write cycle)
EB0, EB1 de-asserted to CKO rising edge (write cycle)
D[15:0] input setup to 3rd CKO rising edge after EB0 or EB1
asserted low (write cycle) (see note 1)
D[15:0] input hold from 3rd CKO rising edge after EB0 or EB1
asserted low (write cycle)
OE, EB0, EB1 setup to CKO rising edge (read cycle)
OE, EB0, EB1 hold to CKO rising edge (read cycle)
D[15:0] output delay from OE, EB0, EB1 falling edge
(read cycle)
1st CKO rising edge after EB0 or EB1 asserted low to D[15:0]
valid for MCLK = BCLK (read cycle)
1st CKO rising edge after EB0 or EB1 asserted low to D[15:0]
valid for MCLK = BCLK ÷ 2 (read cycle)
1st CKO rising edge after EB0 or EB1 asserted low to D[15:0]
valid for MCLK = BCLK ÷ 3 (read cycle)
1st CKO rising edge after EB0 or EB1 asserted low to D[15:0]
valid for MCLK = BCLK ÷ 4 (read cycle)
CKO rising edge to D[15:0] output in Hi-Z (read cycle)
Table 6-11: Motorola REDCAP2 Interface Timing
Parameter
Revision 10.3
1/f
Min
26
26
10
13
15
23
CKO
1
0
8
1
1
1
1
1
4
4
2.0V
4.5CKO
7CKO +
8.5CKO
9CKO +
Max
+ 7
+ 8
17
29
10
11
31
1/f
Min
26
26
10
13
15
CKO
1
0
8
1
4
0
8
0
0
3
1
3.3V
4.5CKO +
6.5CKO +
9.5CKO +
11.5CKO
Max
+ 20
17
10
20
20
20
11
X31B-A-001-10
S1D13706
Page 45
Units
T
T
T
T
MHz
ns
ns
ns
ns
ns
CKO
CKO
CKO
CKO
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns

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