S1D13706F00A200 Epson, S1D13706F00A200 Datasheet - Page 59

• Manufacturer Part Number: S1D13706F00A200
• Description: LCD Drivers (QVGA) 320x240 LCD Controller @ 8bpp
• Manufacturer: Epson

Specifications of S1D13706F00A200

• Maximum Clock Frequency: 33 MHz
• Operating Supply Voltage: 1.8 V to 2.2 V, 3 V to 3.6 V
• Maximum Operating Temperature: + 85 C
• Package / Case: TQFP-100
• Attached Touch Screen: No
• Minimum Operating Temperature: - 40 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Epson Research and Development
Vancouver Design Center
6.4.4 Single Color 4-Bit Panel Timing
VDP
VNDP
HDP
HNDP
Hardware Functional Specification
Issue Date: 2008/12/16
- FPSHIFT uses extended low states in order to process 8 pixels in 6 FPSHIFT clocks
- Ts = Pixel clock period (PCLK)
- Diagram drawn with 2 FPLINE vertical blank period
- Example timing for a 320x240 panel
Notes:
DRDY (MOD)
DRDY (MOD)
= Vertical Display Period
= (REG[1Dh] bits 1-0, REG[1Ch] bits 7-0) + 1 Lines
= Vertical Non-Display Period
= VT - VDP
= (REG[19h] bits 1-0, REG[18h] bits 7-0) - (REG[1Dh] bits 1-0, REG[1Ch] bits 7-0) Lines
= Horizontal Display Period
= ((REG[14h] bits 6-0) + 1) x 8Ts
= Horizontal Non-Display Period
= HT - HDP
= (((REG[12h] bits 6-0) + 1) x 8Ts) - (((REG[14h] bits 6-0) + 1) x 8Ts)
FPDAT[7:4]
FPFRAME
FPSHIFT
FPDAT7
FPDAT6
FPDAT5
FPDAT4
FPLINE
FPLINE
Invalid
Invalid
Invalid
Invalid
Invalid
.5Ts
1-R1
1-B1
1-R2
Figure 6-19: Single Color 4-Bit Panel Timing
1-G1
.5Ts
.5Ts
1-G2
1-B2
1-R3
1-G3
LINE1
.5Ts
.5Ts
1-B3
1-R4
1-G4
1-B4
.5Ts
LINE2
.5Ts
.5Ts
Revision 10.3
LINE3
.5Ts
.5Ts
.5Ts
VDP
LINE4
2.5Ts
HDP
.5Ts
.5Ts
.5Ts
LINE239 LINE240
.5Ts
.5Ts
.5Ts
1-B319
1-R320
1-G320
1-B320
VNDP
Invalid
Invalid
Invalid
Invalid
Invalid
HNDP
LINE1
.5Ts
LINE2
X31B-A-001-10
S1D13706
Page 59